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First running port

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This commit is contained in:
Peter Antypas 2020-10-09 12:16:06 -07:00
parent f88b84fb5c
commit 423c0dc073
19 changed files with 137 additions and 143 deletions
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22
latest/Firmware/.cproject
View File

@ -329,7 +329,7 @@
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<entry excluding="startup/startup_stm32l412xx.S|Drivers/CMSIS_Old|Drivers/STM32L4xx_HAL_Driver_Old|Src/main.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> <entry excluding="Drivers/STM32L4xx_HAL_Driver_Old|Drivers/CMSIS_Old|startup/startup_stm32l412xx.S|Src/main.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries> </sourceEntries>
@ -665,7 +665,7 @@
<sourceEntries> <sourceEntries>
<entry excluding="startup/startup_stm32l412xx.S|Drivers/CMSIS_Old|Drivers/STM32L4xx_HAL_Driver_Old|Src/main.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/> <entry excluding="Drivers/STM32L4xx_HAL_Driver_Old|Drivers/CMSIS_Old|startup/startup_stm32l412xx.S|Src/main.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
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@ -777,7 +777,7 @@
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@ -791,7 +791,7 @@
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@ -883,6 +883,8 @@
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<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/CMSIS/Include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/CMSIS/Device/ST/STM32L4xx/Include}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/CMSIS/Device/ST/STM32L4xx/Include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/portable/GCC/ARM_CM4F}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/portable/GCC/ARM_CM4F}&quot;"/>
@ -891,8 +893,6 @@
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Inc/bsp}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Inc/bsp}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/CMSIS/Include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Inc}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/STM32L4xx_HAL_Driver/Inc}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/STM32L4xx_HAL_Driver/Inc}&quot;"/>
@ -913,6 +913,8 @@
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<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Inc}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/portable/GCC/ARM_CM4F}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/portable/GCC/ARM_CM4F}&quot;"/>
@ -923,8 +925,6 @@
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/CMSIS/Device/ST/STM32L4xx/Include}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/CMSIS/Device/ST/STM32L4xx/Include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/CMSIS/Include}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/STM32L4xx_HAL_Driver/Inc}&quot;"/> <listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Drivers/STM32L4xx_HAL_Driver/Inc}&quot;"/>
</option> </option>
@ -1013,7 +1013,7 @@
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@ -1125,7 +1125,7 @@
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@ -1355,7 +1355,7 @@
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</sourceEntries> </sourceEntries>

4
latest/Firmware/.settings/language.settings.xml
View File

@ -59,7 +59,7 @@
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/> <provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1857589726391058780" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true"> <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1852595269257746636" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/> <language-scope id="org.eclipse.cdt.core.gcc"/>
@ -83,7 +83,7 @@
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/> <provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1875525642069438555" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true"> <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1805734684583076923" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/> <language-scope id="org.eclipse.cdt.core.gcc"/>

2
latest/Firmware/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h
View File

@ -64,7 +64,7 @@
!defined (STM32L496xx) && !defined (STM32L4A6xx) && \ !defined (STM32L496xx) && !defined (STM32L4A6xx) && \
!defined (STM32L4P5xx) && !defined (STM32L4Q5xx) && \ !defined (STM32L4P5xx) && !defined (STM32L4Q5xx) && \
!defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)
/* #define STM32L412xx */ /*!< STM32L412xx Devices */ #define STM32L412xx /*!< STM32L412xx Devices */
/* #define STM32L422xx */ /*!< STM32L422xx Devices */ /* #define STM32L422xx */ /*!< STM32L422xx Devices */
/* #define STM32L431xx */ /*!< STM32L431xx Devices */ /* #define STM32L431xx */ /*!< STM32L431xx Devices */
/* #define STM32L432xx */ /*!< STM32L432xx Devices */ /* #define STM32L432xx */ /*!< STM32L432xx Devices */

3
latest/Firmware/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
View File

@ -856,8 +856,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#define FLASH_PAGE_SIZE ((uint32_t)0x800) #define FLASH_PAGE_SIZE ((uint32_t)0x800)
#endif #endif
//#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
#define FLASH_TIMEOUT_VALUE 1200 // 1200ms
/** /**
* @} * @}
*/ */

6
latest/Firmware/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
View File

@ -256,7 +256,7 @@ __weak void HAL_MspDeInit(void)
* @param TickPriority Tick interrupt priority. * @param TickPriority Tick interrupt priority.
* @retval HAL status * @retval HAL status
*/ */
#if 1
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
@ -290,7 +290,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
/* Return function status */ /* Return function status */
return status; return status;
} }
#endif
/** /**
* @} * @}
*/ */
@ -418,6 +418,7 @@ __weak void HAL_Delay(uint32_t Delay)
* implementations in user file. * implementations in user file.
* @retval None * @retval None
*/ */
#if 0
__weak void HAL_SuspendTick(void) __weak void HAL_SuspendTick(void)
{ {
/* Disable SysTick Interrupt */ /* Disable SysTick Interrupt */
@ -439,6 +440,7 @@ __weak void HAL_ResumeTick(void)
/* Enable SysTick Interrupt */ /* Enable SysTick Interrupt */
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
} }
#endif
/** /**
* @brief Return the HAL revision. * @brief Return the HAL revision.

2
latest/Firmware/FreeRTOS/include/FreeRTOS.h
View File

@ -771,7 +771,7 @@ extern "C" {
#endif #endif
#ifndef portDONT_DISCARD #ifndef portDONT_DISCARD
#define portDONT_DISCARD __attribute__((used)) #define portDONT_DISCARD
#endif #endif
#ifndef configUSE_TIME_SLICING #ifndef configUSE_TIME_SLICING

1
latest/Firmware/FreeRTOS/portable/GCC/ARM_CM4F/port.c
View File

@ -486,7 +486,6 @@ void xPortPendSVHandler( void )
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void xPortSysTickHandler( void ) void xPortSysTickHandler( void )
//void SysTick_Handler(void)
{ {
/* The SysTick runs at the lowest interrupt priority, so when this interrupt /* The SysTick runs at the lowest interrupt priority, so when this interrupt
executes all interrupts must be unmasked. There is therefore no need to executes all interrupts must be unmasked. There is therefore no need to

1
latest/Firmware/FreeRTOS/portable/GCC/ARM_CM4F/portmacro.h
View File

@ -52,7 +52,6 @@ extern "C" {
#define portSTACK_TYPE uint32_t #define portSTACK_TYPE uint32_t
#define portBASE_TYPE long #define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t; typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t; typedef long BaseType_t;
typedef unsigned long UBaseType_t; typedef unsigned long UBaseType_t;

2
latest/Firmware/FreeRTOS/tasks.c
View File

@ -2944,7 +2944,7 @@ BaseType_t xSwitchRequired = pdFALSE;
#endif /* configUSE_APPLICATION_TASK_TAG */ #endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vTaskSwitchContext( void ) __attribute__((used)) void vTaskSwitchContext( void )
{ {
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
{ {

7
latest/Firmware/Inc/FreeRTOSConfig.h
View File

@ -59,7 +59,7 @@
#define configSUPPORT_STATIC_ALLOCATION 1 #define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 1 #define configSUPPORT_DYNAMIC_ALLOCATION 1
#define configUSE_IDLE_HOOK 0 #define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 1 #define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( SystemCoreClock ) #define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ((TickType_t)1000) #define configTICK_RATE_HZ ((TickType_t)1000)
#define configMAX_PRIORITIES ( 7 ) #define configMAX_PRIORITIES ( 7 )
@ -72,6 +72,11 @@
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
#define configCHECK_FOR_STACK_OVERFLOW 1 #define configCHECK_FOR_STACK_OVERFLOW 1
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH 256
/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */ /* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */
/* Defaults to size_t for backward compatibility, but can be changed /* Defaults to size_t for backward compatibility, but can be changed

2
latest/Firmware/STM32L412KBUx_FLASH.ld
View File

@ -55,7 +55,7 @@ ENTRY(Reset_Handler)
/* Highest address of the user mode stack */ /* Highest address of the user mode stack */
_estack = 0x2000A000; /* end of RAM */ _estack = 0x2000A000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */ /* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x1000; /* required amount of heap */ _Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */ _Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */ /* Specify the memory areas */

4
latest/Firmware/Src/EventQueue.cpp
View File

@ -28,7 +28,7 @@
#include "queue.h" #include "queue.h"
#include "task.h" #include "task.h"
#define EVENT_QUEUE_SIZE 10 #define EVENT_QUEUE_SIZE 40
static Event __queue[EVENT_QUEUE_SIZE]; static Event __queue[EVENT_QUEUE_SIZE];
@ -84,7 +84,7 @@ void EventQueue::dispatch()
{ {
Event e; Event e;
while ( xQueueReceive(mQueueHandle, &e, 0) == pdTRUE ) while ( xQueueReceive(mQueueHandle, &e, 10) == pdTRUE )
{ {
for ( map<EventConsumer*, uint32_t>::iterator c = mConsumers.begin(); c != mConsumers.end(); ++c ) for ( map<EventConsumer*, uint32_t>::iterator c = mConsumers.begin(); c != mConsumers.end(); ++c )
{ {

2
latest/Firmware/Src/SystickTimer.cpp
View File

@ -58,7 +58,7 @@ extern "C"
{ {
void HAL_SYSTICK_Callback() void HAL_SYSTICK_Callback()
{ {
SystickTimer::instance().onTick(); //SystickTimer::instance().onTick();
} }
} }

22
latest/Firmware/Src/bsp/bsp_5_2.cpp
View File

@ -33,8 +33,10 @@ IWDG_HandleTypeDef hiwdg;
UART_HandleTypeDef huart2; UART_HandleTypeDef huart2;
UART_HandleTypeDef huart1; UART_HandleTypeDef huart1;
TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim2;
TIM_HandleTypeDef htim6;
void SystemClock_Config(); void SystemClock_Config();
void bsp_init_hw_tick();
char_input_cb gnssInputCallback = nullptr; char_input_cb gnssInputCallback = nullptr;
char_input_cb terminalInputCallback = nullptr; char_input_cb terminalInputCallback = nullptr;
@ -82,7 +84,7 @@ extern "C"
{ {
asm("BKPT 0"); asm("BKPT 0");
//printf_serial_now("[ERROR]\r\n"); printf_serial_now("[ERROR %d]\r\n", i);
//printf_serial_now("[ERROR] ***** System error handler resetting *****\r\n"); //printf_serial_now("[ERROR] ***** System error handler resetting *****\r\n");
//NVIC_SystemReset(); //NVIC_SystemReset();
} }
@ -293,7 +295,7 @@ void SystemClock_Config()
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/* SysTick_IRQn interrupt configuration */ /* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0); HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
} }
void gpio_pin_init() void gpio_pin_init()
@ -319,23 +321,23 @@ void HAL_MspInit(void)
__HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE();
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); //HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* System interrupt init*/ /* System interrupt init*/
/* MemoryManagement_IRQn interrupt configuration */ /* MemoryManagement_IRQn interrupt configuration */
HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); //HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
/* BusFault_IRQn interrupt configuration */ /* BusFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); //HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
/* UsageFault_IRQn interrupt configuration */ /* UsageFault_IRQn interrupt configuration */
HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); //HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
/* SVCall_IRQn interrupt configuration */ /* SVCall_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); //HAL_NVIC_SetPriority(SVCall_IRQn, 15, 0);
/* DebugMonitor_IRQn interrupt configuration */ /* DebugMonitor_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); //HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
/* PendSV_IRQn interrupt configuration */ /* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
/* SysTick_IRQn interrupt configuration */ /* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); //HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
/* USER CODE BEGIN MspInit 1 */ /* USER CODE BEGIN MspInit 1 */

16
latest/Firmware/Src/freertos.c
View File

@ -55,6 +55,9 @@
/* GetIdleTaskMemory prototype (linked to static allocation support) */ /* GetIdleTaskMemory prototype (linked to static allocation support) */
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
/* GetTimerTaskMemory prototype (linked to static allocation support) */
void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */ /* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
static StaticTask_t xIdleTaskTCBBuffer; static StaticTask_t xIdleTaskTCBBuffer;
static StackType_t xIdleStack[configMINIMAL_STACK_SIZE]; static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
@ -68,6 +71,19 @@ void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackTy
} }
/* USER CODE END GET_IDLE_TASK_MEMORY */ /* USER CODE END GET_IDLE_TASK_MEMORY */
/* USER CODE BEGIN GET_TIMER_TASK_MEMORY */
static StaticTask_t xTimerTaskTCBBuffer;
static StackType_t xTimerStack[configTIMER_TASK_STACK_DEPTH];
void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
{
*ppxTimerTaskTCBBuffer = &xTimerTaskTCBBuffer;
*ppxTimerTaskStackBuffer = &xTimerStack[0];
*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
/* place for user code */
}
/* USER CODE END GET_TIMER_TASK_MEMORY */
/* Private application code --------------------------------------------------*/ /* Private application code --------------------------------------------------*/
/* USER CODE BEGIN Application */ /* USER CODE BEGIN Application */

106
latest/Firmware/Src/main.cpp
View File

@ -29,6 +29,8 @@
#include "printf_serial.h" #include "printf_serial.h"
#include "FreeRTOS.h" #include "FreeRTOS.h"
#include "task.h" #include "task.h"
#include "timers.h"
void fireTestPacket() void fireTestPacket()
{ {
@ -68,45 +70,58 @@ void determineCauseOfReset()
__HAL_RCC_CLEAR_RESET_FLAGS(); __HAL_RCC_CLEAR_RESET_FLAGS();
} }
TimerHandle_t timerHandle1, timerHandle2;
StaticTimer_t timer1, timer2;
extern "C"{
void on1sec(TimerHandle_t handle)
{
Event e(ONE_SEC_TIMER_EVENT);
EventQueue::instance().push(e);
}
void on1min(TimerHandle_t handle)
{
Event e(ONE_MIN_TIMER_EVENT);
EventQueue::instance().push(e);
}
}
void mainTask(void *params) void mainTask(void *params)
{ {
//uint32_t counter = 0; EventQueue::instance().init();
Configuration::instance().init();
CommandProcessor::instance().init();
DataTerminal::instance().init();
//bsp_start_wdt(); RXPacketProcessor packetProcessor;
#if not defined CALIBRATION_MODE && not defined TX_TEST_MODE
GPS::instance().init();
GPS::instance().enable();
#endif
#ifdef ENABLE_TX
TXPacketPool::instance().init();
TXScheduler::instance().init();
#endif
RadioManager::instance().init();
RadioManager::instance().start();
timerHandle1 = xTimerCreateStatic("1sec", 1000, pdTRUE, NULL, on1sec, &timer1);
xTimerStart(timerHandle1, 10);
timerHandle2 = xTimerCreateStatic("1min", 1000, pdTRUE, NULL, on1min, &timer2);
xTimerStart(timerHandle2, 10);
// We're getting a very high rate of interrupts, so there's no need to dispatch events every time
while (1) while (1)
{ {
//__WFI();
vTaskDelay(10);
//++counter;
//if ( counter % 100 == 0 )
//{
//counter = 1;
//bsp_refresh_wdt();
EventQueue::instance().dispatch(); EventQueue::instance().dispatch();
//}
} }
} }
class Ticker : EventConsumer
{
public:
Ticker()
{
EventQueue::instance().addObserver(this, ONE_SEC_TIMER_EVENT);
}
void processEvent(const Event &e)
{
++__t;
printf_serial_now("Tick %d\r\n", __t);
}
private:
int __t = 0;
};
extern "C" { extern "C" {
__attribute__((used)) void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName ) __attribute__((used)) void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName )
{ {
@ -114,45 +129,20 @@ __attribute__((used)) void vApplicationStackOverflowHook( TaskHandle_t xTask, si
asm("BKPT 0"); asm("BKPT 0");
} }
__attribute__((used)) void vApplicationTickHook()
{
asm("BKPT 0");
} }
}
int main(void) int main(void)
{ {
//*(uint8_t *)0xe000ed08 |= 2; *(uint8_t *)0xe000ed08 |= 2;
bsp_hw_init(); bsp_hw_init();
EventQueue::instance().init();
SystickTimer::instance();
Ticker t;
//Configuration::instance().init();
//CommandProcessor::instance().init();
//DataTerminal::instance().init();
//RXPacketProcessor packetProcessor;
#if not defined CALIBRATION_MODE && not defined TX_TEST_MODE
//GPS::instance().init();
//GPS::instance().enable();
#endif
#ifdef ENABLE_TX
//TXPacketPool::instance().init();
//TXScheduler::instance().init();
#endif
//RadioManager::instance().init();
//RadioManager::instance().start();
TaskHandle_t xHandle; TaskHandle_t xHandle;
if ( xTaskCreate(mainTask, "main", 256u, NULL, tskIDLE_PRIORITY+1, &xHandle) != pdPASS ) if ( xTaskCreate(mainTask, "main", 2048u, NULL, tskIDLE_PRIORITY+4, &xHandle) != pdPASS )
{ {
asm("BKPT 0"); asm("BKPT 0");
} }
xPortStartScheduler(); vTaskStartScheduler();
asm("BKPT 0");
return 1;
} }

3
latest/Firmware/Src/stm32l4xx_hal_timebase_tim.c
View File

@ -48,7 +48,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
uint32_t pFLatency; uint32_t pFLatency;
/*Configure the TIM6 IRQ priority */ /*Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_IRQn, 5,0);//TickPriority ,0); HAL_NVIC_SetPriority(TIM6_IRQn,TickPriority ,0);
/* Enable the TIM6 global Interrupt */ /* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_IRQn); HAL_NVIC_EnableIRQ(TIM6_IRQn);
@ -131,7 +131,6 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
/* USER CODE END Callback 0 */ /* USER CODE END Callback 0 */
if (htim->Instance == TIM6) { if (htim->Instance == TIM6) {
HAL_IncTick(); HAL_IncTick();
HAL_SYSTICK_IRQHandler();
} }
/* USER CODE BEGIN Callback 1 */ /* USER CODE BEGIN Callback 1 */

73
latest/Firmware/Src/system_stm32l4xx.c
View File

@ -2,8 +2,6 @@
****************************************************************************** ******************************************************************************
* @file system_stm32l4xx.c * @file system_stm32l4xx.c
* @author MCD Application Team * @author MCD Application Team
* @version V1.2.0
* @date 28-October-2016
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
* *
* This file provides two functions and one global variable to be called from * This file provides two functions and one global variable to be called from
@ -68,29 +66,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -110,15 +92,15 @@
#include "stm32l4xx.h" #include "stm32l4xx.h"
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (MSI_VALUE) #if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */ #endif /* MSI_VALUE */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/** /**
@ -141,7 +123,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
/* #define VECT_TAB_SRAM */ /* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0000 /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
/******************************************************************************/ /******************************************************************************/
/** /**
@ -167,12 +149,12 @@
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 4000000; uint32_t SystemCoreClock = 4000000U;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \ const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
4000000, 8000000, 16000000, 24000000, 32000000, 48000000}; 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
/** /**
* @} * @}
*/ */
@ -201,24 +183,25 @@ void SystemInit(void)
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif #endif
/* Reset the RCC clock configuration to the default reset state ------------*/ /* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */ /* Set MSION bit */
RCC->CR |= RCC_CR_MSION; RCC->CR |= RCC_CR_MSION;
/* Reset CFGR register */ /* Reset CFGR register */
RCC->CFGR = 0x00000000; RCC->CFGR = 0x00000000U;
/* Reset HSEON, CSSON , HSION, and PLLON bits */ /* Reset HSEON, CSSON , HSION, and PLLON bits */
RCC->CR &= (uint32_t)0xEAF6FFFF; RCC->CR &= 0xEAF6FFFFU;
/* Reset PLLCFGR register */ /* Reset PLLCFGR register */
RCC->PLLCFGR = 0x00001000; RCC->PLLCFGR = 0x00001000U;
/* Reset HSEBYP bit */ /* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF; RCC->CR &= 0xFFFBFFFFU;
/* Disable all interrupts */ /* Disable all interrupts */
RCC->CIER = 0x00000000; RCC->CIER = 0x00000000U;
/* Configure the Vector Table location add offset address ------------------*/ /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM #ifdef VECT_TAB_SRAM
@ -272,16 +255,16 @@ void SystemInit(void)
*/ */
void SystemCoreClockUpdate(void) void SystemCoreClockUpdate(void)
{ {
uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2; uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;
/* Get MSI Range frequency--------------------------------------------------*/ /* Get MSI Range frequency--------------------------------------------------*/
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
{ /* MSISRANGE from RCC_CSR applies */ { /* MSISRANGE from RCC_CSR applies */
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8; msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
} }
else else
{ /* MSIRANGE from RCC_CR applies */ { /* MSIRANGE from RCC_CR applies */
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4; msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
} }
/*MSI frequency range in HZ*/ /*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange]; msirange = MSIRangeTable[msirange];
@ -306,7 +289,7 @@ void SystemCoreClockUpdate(void)
SYSCLK = PLL_VCO / PLLR SYSCLK = PLL_VCO / PLLR
*/ */
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ; pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
switch (pllsource) switch (pllsource)
{ {
@ -322,8 +305,8 @@ void SystemCoreClockUpdate(void)
pllvco = (msirange / pllm); pllvco = (msirange / pllm);
break; break;
} }
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2; pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
SystemCoreClock = pllvco/pllr; SystemCoreClock = pllvco/pllr;
break; break;
@ -333,7 +316,7 @@ void SystemCoreClockUpdate(void)
} }
/* Compute HCLK clock frequency --------------------------------------------*/ /* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */ /* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */ /* HCLK clock frequency */
SystemCoreClock >>= tmp; SystemCoreClock >>= tmp;
} }

2
latest/Firmware/openocd-flash-l412-release-build.cfg
View File

@ -2,7 +2,7 @@ source [find interface/stlink.cfg]
transport select hla_swd transport select hla_swd
source [find target/stm32l4x.cfg] source [find target/stm32l4x.cfg]
adapter speed 950 #adapter speed 350
#reset_config srst_nogate #reset_config srst_nogate
#adapter srst delay 100 #adapter srst delay 100