mirror of
https://github.com/peterantypas/maiana.git
synced 2025-05-27 21:00:24 -07:00
Added bootloader
This commit is contained in:
Peter Antypas
parent
fc8a4f8c29
commit
5d8df7084a
367
bootloader/.cproject
Normal file
367
bootloader/.cproject
Normal file
@ -0,0 +1,367 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
|
||||
<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384." name="/" resourcePath="">
|
||||
<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.779139005" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.297303722" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.size" valueType="enumerated"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.641170094" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.763090641" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.582804454" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.1250835462" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.90053131" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.max" valueType="enumerated"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.1323360289" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.1970638319" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1722289431" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn.2091376608" name="Enable extra warnings (-Wextra)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding.1945972775" name="Assume freestanding environment (-ffreestanding)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nomoveloopinvariants.894528177" name="Disable loop invariant move (-fno-move-loop-invariants)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nomoveloopinvariants" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.lto.1888203068" name="Link-time optimizer (-flto)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.lto" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.995392406" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="GNU Tools for ARM Embedded Processors" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.1472490856" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.architecture" value="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.arm" valueType="enumerated"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.1563625473" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.thumb" valueType="enumerated"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.921262819" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.1889275046" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1902124834" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.1562117678" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" value="ar" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1176890747" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.1139346323" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.292733201" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.549922782" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1556557251" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.1513453150" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.1541191683" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.1199165538" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
|
||||
<builder buildPath="${workspace_loc:/bootloader}/Debug" id="ilg.gnuarmeclipse.managedbuild.cross.builder.1394022897" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.566843426" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.1717511739" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.195616941" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""../include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/cmsis""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/stm32f3-stdperiph""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1106777675" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="USE_FULL_ASSERT"/>
|
||||
<listOptionValue builtIn="false" value="TRACE"/>
|
||||
<listOptionValue builtIn="false" value="OS_USE_TRACE_SEMIHOSTING_DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="STM32F30X"/>
|
||||
<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.1668120233" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1084938448" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.1242280671" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""../include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/cmsis""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/stm32f3-stdperiph""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.786285587" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="USE_FULL_ASSERT"/>
|
||||
<listOptionValue builtIn="false" value="TRACE"/>
|
||||
<listOptionValue builtIn="false" value="OS_USE_TRACE_SEMIHOSTING_DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="STM32F30X"/>
|
||||
<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.1117831188" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.20925106" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.1939305627" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""../include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/cmsis""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/stm32f3-stdperiph""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.2122341131" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.402088567" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit.2113957828" name="Do not use _cxa_atexit() (-fno-use-cxa-atexit)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics.676755285" name="Do not use thread-safe statics (-fno-threadsafe-statics)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.152288333" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="USE_FULL_ASSERT"/>
|
||||
<listOptionValue builtIn="false" value="TRACE"/>
|
||||
<listOptionValue builtIn="false" value="OS_USE_TRACE_SEMIHOSTING_DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="STM32F30X"/>
|
||||
<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.342589781" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.153714803" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.546512212" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths.1429138300" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths" valueType="libPaths">
|
||||
<listOptionValue builtIn="false" value=""../ldscripts""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile.304161173" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="mem.ld"/>
|
||||
<listOptionValue builtIn="false" value="libs.ld"/>
|
||||
<listOptionValue builtIn="false" value="sections.ld"/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart.1414052915" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano.537391465" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.602550790" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.939831071" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.1929672216" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
|
||||
<listOptionValue builtIn="false" value=""../ldscripts""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.1218119512" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="mem.ld"/>
|
||||
<listOptionValue builtIn="false" value="libs.ld"/>
|
||||
<listOptionValue builtIn="false" value="sections.ld"/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart.377625095" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano.931602761" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano" value="true" valueType="boolean"/>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.55228258" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
</inputType>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.552177129" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.983790132" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1772782935" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.1509415771" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.710759655" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.951578855" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.2082163524" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.179187839" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1695808298" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.608550899" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1243351524" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<fileInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384.system/src/newlib/_startup.c" name="_startup.c" rcbsApplicability="disable" resourcePath="system/src/newlib/_startup.c" toolsToInvoke="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1084938448.2095902783">
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1084938448.2095902783" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1084938448">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.1418566073" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="USE_FULL_ASSERT"/>
|
||||
<listOptionValue builtIn="false" value="TRACE"/>
|
||||
<listOptionValue builtIn="false" value="OS_USE_TRACE_SEMIHOSTING_DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="STM32F30X"/>
|
||||
<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
<listOptionValue builtIn="false" value="OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS"/>
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.486394802" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
|
||||
</tool>
|
||||
</fileInfo>
|
||||
<sourceEntries>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
|
||||
<entry excluding="src/stm32f3-stdperiph/stm32f30x_wwdg.c|src/stm32f3-stdperiph/stm32f30x_tim.c|src/stm32f3-stdperiph/stm32f30x_syscfg.c|src/stm32f3-stdperiph/stm32f30x_spi.c|src/stm32f3-stdperiph/stm32f30x_rtc.c|src/stm32f3-stdperiph/stm32f30x_pwr.c|src/stm32f3-stdperiph/stm32f30x_opamp.c|src/stm32f3-stdperiph/stm32f30x_iwdg.c|src/stm32f3-stdperiph/stm32f30x_i2c.c|src/stm32f3-stdperiph/stm32f30x_exti.c|src/stm32f3-stdperiph/stm32f30x_dma.c|src/stm32f3-stdperiph/stm32f30x_dbgmcu.c|src/stm32f3-stdperiph/stm32f30x_dac.c|src/stm32f3-stdperiph/stm32f30x_crc.c|src/stm32f3-stdperiph/stm32f30x_comp.c|src/stm32f3-stdperiph/stm32f30x_can.c|src/stm32f3-stdperiph/stm32f30x_adc.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="system"/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779" name="Release" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release">
|
||||
<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779." name="/" resourcePath="">
|
||||
<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release.518006428" name="Cross ARM GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.release">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1692724472" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.size" valueType="enumerated"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1087294935" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.491273050" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.1991216570" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.1916071619" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.104568058" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.815972156" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.64995568" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1648488408" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn.479824917" name="Enable extra warnings (-Wextra)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding.350939496" name="Assume freestanding environment (-ffreestanding)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.lto.166203611" name="Link-time optimizer (-flto)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.lto" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.400922669" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="GNU Tools for ARM Embedded Processors" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.998226754" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.architecture" value="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.arm" valueType="enumerated"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.301974969" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.thumb" valueType="enumerated"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.1362650022" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.568674475" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1363298789" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.174728394" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" value="ar" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1578996806" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.868870790" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.1883388883" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.2139594474" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.501194038" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.496296578" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.271996851" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.1488607389" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
|
||||
<builder buildPath="${workspace_loc:/bootloader}/Release" id="ilg.gnuarmeclipse.managedbuild.cross.builder.1901609664" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.1421847376" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.883043863" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.310921965" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""../include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/cmsis""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/stm32f3-stdperiph""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.144991485" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="OS_USE_TRACE_SEMIHOSTING_DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="STM32F30X"/>
|
||||
<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.229929664" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1755431883" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.1120079433" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""../include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/cmsis""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/stm32f3-stdperiph""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.1096112" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="OS_USE_TRACE_SEMIHOSTING_DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="STM32F30X"/>
|
||||
<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.2099000360" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.2099986827" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.349120055" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""../include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/cmsis""/>
|
||||
<listOptionValue builtIn="false" value=""../system/include/stm32f3-stdperiph""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.1030862937" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.1795759378" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit.297652646" name="Do not use _cxa_atexit() (-fno-use-cxa-atexit)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics.1768108089" name="Do not use thread-safe statics (-fno-threadsafe-statics)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.1990612701" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="OS_USE_TRACE_SEMIHOSTING_DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="STM32F30X"/>
|
||||
<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1946201835" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.849014063" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.2058190702" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths.1708567874" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths" valueType="libPaths">
|
||||
<listOptionValue builtIn="false" value=""../ldscripts""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile.1592492411" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="mem.ld"/>
|
||||
<listOptionValue builtIn="false" value="libs.ld"/>
|
||||
<listOptionValue builtIn="false" value="sections.ld"/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart.1396621719" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano.514177416" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.2066483688" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.1473280698" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.1527249100" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
|
||||
<listOptionValue builtIn="false" value=""../ldscripts""/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.1281480348" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="mem.ld"/>
|
||||
<listOptionValue builtIn="false" value="libs.ld"/>
|
||||
<listOptionValue builtIn="false" value="sections.ld"/>
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart.1143271467" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano.1595923428" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano" value="true" valueType="boolean"/>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.1234223951" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
</inputType>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.1723287228" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1030039215" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.845181077" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.512586375" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.552807057" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.175117674" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.1208659325" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1471235859" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1024517961" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.331004091" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.1821018668" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<fileInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779.system/src/newlib/_startup.c" name="_startup.c" rcbsApplicability="disable" resourcePath="system/src/newlib/_startup.c" toolsToInvoke="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1755431883.604740538">
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1755431883.604740538" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1755431883">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.1949895984" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="OS_USE_TRACE_SEMIHOSTING_DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="STM32F30X"/>
|
||||
<listOptionValue builtIn="false" value="USE_STDPERIPH_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
<listOptionValue builtIn="false" value="OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS"/>
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.1987496571" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
|
||||
</tool>
|
||||
</fileInfo>
|
||||
<sourceEntries>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
|
||||
<entry excluding="src/stm32f3-stdperiph/stm32f30x_wwdg.c|src/stm32f3-stdperiph/stm32f30x_tim.c|src/stm32f3-stdperiph/stm32f30x_syscfg.c|src/stm32f3-stdperiph/stm32f30x_spi.c|src/stm32f3-stdperiph/stm32f30x_rtc.c|src/stm32f3-stdperiph/stm32f30x_pwr.c|src/stm32f3-stdperiph/stm32f30x_opamp.c|src/stm32f3-stdperiph/stm32f30x_iwdg.c|src/stm32f3-stdperiph/stm32f30x_i2c.c|src/stm32f3-stdperiph/stm32f30x_exti.c|src/stm32f3-stdperiph/stm32f30x_dma.c|src/stm32f3-stdperiph/stm32f30x_dbgmcu.c|src/stm32f3-stdperiph/stm32f30x_dac.c|src/stm32f3-stdperiph/stm32f30x_crc.c|src/stm32f3-stdperiph/stm32f30x_comp.c|src/stm32f3-stdperiph/stm32f30x_can.c|src/stm32f3-stdperiph/stm32f30x_adc.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="system"/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule moduleId="ilg.gnuarmeclipse.managedbuild.packs"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="bootloader.ilg.gnuarmeclipse.managedbuild.cross.target.elf.292954013" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779;ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1755431883;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.2099000360">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1084938448;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.1117831188">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.20925106;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.342589781">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779;ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779.;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.2099986827;ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.1946201835">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
<configuration configurationName="Debug">
|
||||
<resource resourceType="PROJECT" workspacePath="/bootloader"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Release">
|
||||
<resource resourceType="PROJECT" workspacePath="/bootloader"/>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
|
||||
</cproject>
|
||||
27
bootloader/.project
Normal file
27
bootloader/.project
Normal file
@ -0,0 +1,27 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>bootloader</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
25
bootloader/.settings/language.settings.xml
Normal file
25
bootloader/.settings/language.settings.xml
Normal file
@ -0,0 +1,25 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.156443384" name="Debug">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1415213990552700957" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
</extension>
|
||||
</configuration>
|
||||
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.release.1743920779" name="Release">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1414503461445076851" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
90
bootloader/Debug/makefile
Normal file
90
bootloader/Debug/makefile
Normal file
@ -0,0 +1,90 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
-include ../makefile.init
|
||||
|
||||
RM := rm -rf
|
||||
|
||||
# All of the sources participating in the build are defined here
|
||||
-include sources.mk
|
||||
-include system/src/stm32f3-stdperiph/subdir.mk
|
||||
-include system/src/newlib/subdir.mk
|
||||
-include system/src/diag/subdir.mk
|
||||
-include system/src/cortexm/subdir.mk
|
||||
-include system/src/cmsis/subdir.mk
|
||||
-include src/subdir.mk
|
||||
-include subdir.mk
|
||||
-include objects.mk
|
||||
|
||||
ifneq ($(MAKECMDGOALS),clean)
|
||||
ifneq ($(strip $(CC_DEPS)),)
|
||||
-include $(CC_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C++_DEPS)),)
|
||||
-include $(C++_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C_UPPER_DEPS)),)
|
||||
-include $(C_UPPER_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CXX_DEPS)),)
|
||||
-include $(CXX_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(ASM_DEPS)),)
|
||||
-include $(ASM_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S_UPPER_DEPS)),)
|
||||
-include $(S_UPPER_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C_DEPS)),)
|
||||
-include $(C_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CPP_DEPS)),)
|
||||
-include $(CPP_DEPS)
|
||||
endif
|
||||
endif
|
||||
|
||||
-include ../makefile.defs
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
SECONDARY_FLASH += \
|
||||
bootloader.bin \
|
||||
|
||||
SECONDARY_SIZE += \
|
||||
bootloader.siz \
|
||||
|
||||
|
||||
# All Target
|
||||
all: bootloader.elf secondary-outputs
|
||||
|
||||
# Tool invocations
|
||||
bootloader.elf: $(OBJS) $(USER_OBJS)
|
||||
@echo 'Building target: $@'
|
||||
@echo 'Invoking: Cross ARM C++ Linker'
|
||||
arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -T mem.ld -T libs.ld -T sections.ld -nostartfiles -Xlinker --gc-sections -L"../ldscripts" -Wl,-Map,"bootloader.map" --specs=nano.specs -o "bootloader.elf" $(OBJS) $(USER_OBJS) $(LIBS)
|
||||
@echo 'Finished building target: $@'
|
||||
@echo ' '
|
||||
|
||||
bootloader.bin: bootloader.elf
|
||||
@echo 'Invoking: Cross ARM GNU Create Flash Image'
|
||||
arm-none-eabi-objcopy -O binary "bootloader.elf" "bootloader.bin"
|
||||
@echo 'Finished building: $@'
|
||||
@echo ' '
|
||||
|
||||
bootloader.siz: bootloader.elf
|
||||
@echo 'Invoking: Cross ARM GNU Print Size'
|
||||
arm-none-eabi-size --format=berkeley "bootloader.elf"
|
||||
@echo 'Finished building: $@'
|
||||
@echo ' '
|
||||
|
||||
# Other Targets
|
||||
clean:
|
||||
-$(RM) $(CC_DEPS)$(C++_DEPS)$(OBJS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) bootloader.elf
|
||||
-@echo ' '
|
||||
|
||||
secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_SIZE)
|
||||
|
||||
.PHONY: all clean dependents
|
||||
.SECONDARY:
|
||||
|
||||
-include ../makefile.targets
|
||||
8
bootloader/Debug/objects.mk
Normal file
8
bootloader/Debug/objects.mk
Normal file
@ -0,0 +1,8 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
USER_OBJS :=
|
||||
|
||||
LIBS :=
|
||||
|
||||
36
bootloader/Debug/sources.mk
Normal file
36
bootloader/Debug/sources.mk
Normal file
@ -0,0 +1,36 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
ELF_SRCS :=
|
||||
C_UPPER_SRCS :=
|
||||
CXX_SRCS :=
|
||||
C++_SRCS :=
|
||||
OBJ_SRCS :=
|
||||
CC_SRCS :=
|
||||
ASM_SRCS :=
|
||||
C_SRCS :=
|
||||
CPP_SRCS :=
|
||||
S_UPPER_SRCS :=
|
||||
O_SRCS :=
|
||||
CC_DEPS :=
|
||||
C++_DEPS :=
|
||||
OBJS :=
|
||||
C_UPPER_DEPS :=
|
||||
CXX_DEPS :=
|
||||
SECONDARY_FLASH :=
|
||||
SECONDARY_SIZE :=
|
||||
ASM_DEPS :=
|
||||
S_UPPER_DEPS :=
|
||||
C_DEPS :=
|
||||
CPP_DEPS :=
|
||||
|
||||
# Every subdirectory with source files must be described here
|
||||
SUBDIRS := \
|
||||
src \
|
||||
system/src/cmsis \
|
||||
system/src/cortexm \
|
||||
system/src/diag \
|
||||
system/src/newlib \
|
||||
system/src/stm32f3-stdperiph \
|
||||
|
||||
47
bootloader/Debug/src/subdir.mk
Normal file
47
bootloader/Debug/src/subdir.mk
Normal file
@ -0,0 +1,47 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../src/_write.c \
|
||||
../src/md5.c
|
||||
|
||||
CPP_SRCS += \
|
||||
../src/DataTerminal.cpp \
|
||||
../src/Timer.cpp \
|
||||
../src/main.cpp
|
||||
|
||||
OBJS += \
|
||||
./src/DataTerminal.o \
|
||||
./src/Timer.o \
|
||||
./src/_write.o \
|
||||
./src/main.o \
|
||||
./src/md5.o
|
||||
|
||||
C_DEPS += \
|
||||
./src/_write.d \
|
||||
./src/md5.d
|
||||
|
||||
CPP_DEPS += \
|
||||
./src/DataTerminal.d \
|
||||
./src/Timer.d \
|
||||
./src/main.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
src/%.o: ../src/%.cpp
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C++ Compiler'
|
||||
arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -DDEBUG -DUSE_FULL_ASSERT -DTRACE -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu++11 -fabi-version=0 -fno-exceptions -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
src/%.o: ../src/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -DDEBUG -DUSE_FULL_ASSERT -DTRACE -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
27
bootloader/Debug/system/src/cmsis/subdir.mk
Normal file
27
bootloader/Debug/system/src/cmsis/subdir.mk
Normal file
@ -0,0 +1,27 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/cmsis/system_stm32f30x.c \
|
||||
../system/src/cmsis/vectors_stm32f30x.c
|
||||
|
||||
OBJS += \
|
||||
./system/src/cmsis/system_stm32f30x.o \
|
||||
./system/src/cmsis/vectors_stm32f30x.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/cmsis/system_stm32f30x.d \
|
||||
./system/src/cmsis/vectors_stm32f30x.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/cmsis/%.o: ../system/src/cmsis/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -DDEBUG -DUSE_FULL_ASSERT -DTRACE -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
30
bootloader/Debug/system/src/cortexm/subdir.mk
Normal file
30
bootloader/Debug/system/src/cortexm/subdir.mk
Normal file
@ -0,0 +1,30 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/cortexm/_initialize_hardware.c \
|
||||
../system/src/cortexm/_reset_hardware.c \
|
||||
../system/src/cortexm/exception_handlers.c
|
||||
|
||||
OBJS += \
|
||||
./system/src/cortexm/_initialize_hardware.o \
|
||||
./system/src/cortexm/_reset_hardware.o \
|
||||
./system/src/cortexm/exception_handlers.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/cortexm/_initialize_hardware.d \
|
||||
./system/src/cortexm/_reset_hardware.d \
|
||||
./system/src/cortexm/exception_handlers.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/cortexm/%.o: ../system/src/cortexm/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -DDEBUG -DUSE_FULL_ASSERT -DTRACE -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
27
bootloader/Debug/system/src/diag/subdir.mk
Normal file
27
bootloader/Debug/system/src/diag/subdir.mk
Normal file
@ -0,0 +1,27 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/diag/Trace.c \
|
||||
../system/src/diag/trace_impl.c
|
||||
|
||||
OBJS += \
|
||||
./system/src/diag/Trace.o \
|
||||
./system/src/diag/trace_impl.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/diag/Trace.d \
|
||||
./system/src/diag/trace_impl.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/diag/%.o: ../system/src/diag/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -DDEBUG -DUSE_FULL_ASSERT -DTRACE -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
57
bootloader/Debug/system/src/newlib/subdir.mk
Normal file
57
bootloader/Debug/system/src/newlib/subdir.mk
Normal file
@ -0,0 +1,57 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/newlib/_exit.c \
|
||||
../system/src/newlib/_sbrk.c \
|
||||
../system/src/newlib/_startup.c \
|
||||
../system/src/newlib/_syscalls.c \
|
||||
../system/src/newlib/assert.c
|
||||
|
||||
CPP_SRCS += \
|
||||
../system/src/newlib/_cxx.cpp
|
||||
|
||||
OBJS += \
|
||||
./system/src/newlib/_cxx.o \
|
||||
./system/src/newlib/_exit.o \
|
||||
./system/src/newlib/_sbrk.o \
|
||||
./system/src/newlib/_startup.o \
|
||||
./system/src/newlib/_syscalls.o \
|
||||
./system/src/newlib/assert.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/newlib/_exit.d \
|
||||
./system/src/newlib/_sbrk.d \
|
||||
./system/src/newlib/_startup.d \
|
||||
./system/src/newlib/_syscalls.d \
|
||||
./system/src/newlib/assert.d
|
||||
|
||||
CPP_DEPS += \
|
||||
./system/src/newlib/_cxx.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/newlib/%.o: ../system/src/newlib/%.cpp
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C++ Compiler'
|
||||
arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -DDEBUG -DUSE_FULL_ASSERT -DTRACE -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu++11 -fabi-version=0 -fno-exceptions -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
system/src/newlib/%.o: ../system/src/newlib/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -DDEBUG -DUSE_FULL_ASSERT -DTRACE -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
system/src/newlib/_startup.o: ../system/src/newlib/_startup.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -DDEBUG -DUSE_FULL_ASSERT -DTRACE -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -DOS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"system/src/newlib/_startup.d" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
36
bootloader/Debug/system/src/stm32f3-stdperiph/subdir.mk
Normal file
36
bootloader/Debug/system/src/stm32f3-stdperiph/subdir.mk
Normal file
@ -0,0 +1,36 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_flash.c \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_gpio.c \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_misc.c \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_rcc.c \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_usart.c
|
||||
|
||||
OBJS += \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_flash.o \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_gpio.o \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_misc.o \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_rcc.o \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_usart.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_flash.d \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_gpio.d \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_misc.d \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_rcc.d \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_usart.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/stm32f3-stdperiph/%.o: ../system/src/stm32f3-stdperiph/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -fno-move-loop-invariants -Wall -Wextra -g3 -DDEBUG -DUSE_FULL_ASSERT -DTRACE -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
90
bootloader/Release/makefile
Normal file
90
bootloader/Release/makefile
Normal file
@ -0,0 +1,90 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
-include ../makefile.init
|
||||
|
||||
RM := rm -rf
|
||||
|
||||
# All of the sources participating in the build are defined here
|
||||
-include sources.mk
|
||||
-include system/src/stm32f3-stdperiph/subdir.mk
|
||||
-include system/src/newlib/subdir.mk
|
||||
-include system/src/diag/subdir.mk
|
||||
-include system/src/cortexm/subdir.mk
|
||||
-include system/src/cmsis/subdir.mk
|
||||
-include src/subdir.mk
|
||||
-include subdir.mk
|
||||
-include objects.mk
|
||||
|
||||
ifneq ($(MAKECMDGOALS),clean)
|
||||
ifneq ($(strip $(CC_DEPS)),)
|
||||
-include $(CC_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C++_DEPS)),)
|
||||
-include $(C++_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C_UPPER_DEPS)),)
|
||||
-include $(C_UPPER_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CXX_DEPS)),)
|
||||
-include $(CXX_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(ASM_DEPS)),)
|
||||
-include $(ASM_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(S_UPPER_DEPS)),)
|
||||
-include $(S_UPPER_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C_DEPS)),)
|
||||
-include $(C_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CPP_DEPS)),)
|
||||
-include $(CPP_DEPS)
|
||||
endif
|
||||
endif
|
||||
|
||||
-include ../makefile.defs
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
SECONDARY_FLASH += \
|
||||
bootloader.bin \
|
||||
|
||||
SECONDARY_SIZE += \
|
||||
bootloader.siz \
|
||||
|
||||
|
||||
# All Target
|
||||
all: bootloader.elf secondary-outputs
|
||||
|
||||
# Tool invocations
|
||||
bootloader.elf: $(OBJS) $(USER_OBJS)
|
||||
@echo 'Building target: $@'
|
||||
@echo 'Invoking: Cross ARM C++ Linker'
|
||||
arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -T mem.ld -T libs.ld -T sections.ld -nostartfiles -Xlinker --gc-sections -L"../ldscripts" -Wl,-Map,"bootloader.map" --specs=nano.specs -o "bootloader.elf" $(OBJS) $(USER_OBJS) $(LIBS)
|
||||
@echo 'Finished building target: $@'
|
||||
@echo ' '
|
||||
|
||||
bootloader.bin: bootloader.elf
|
||||
@echo 'Invoking: Cross ARM GNU Create Flash Image'
|
||||
arm-none-eabi-objcopy -O binary "bootloader.elf" "bootloader.bin"
|
||||
@echo 'Finished building: $@'
|
||||
@echo ' '
|
||||
|
||||
bootloader.siz: bootloader.elf
|
||||
@echo 'Invoking: Cross ARM GNU Print Size'
|
||||
arm-none-eabi-size --format=berkeley "bootloader.elf"
|
||||
@echo 'Finished building: $@'
|
||||
@echo ' '
|
||||
|
||||
# Other Targets
|
||||
clean:
|
||||
-$(RM) $(CC_DEPS)$(C++_DEPS)$(OBJS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) bootloader.elf
|
||||
-@echo ' '
|
||||
|
||||
secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_SIZE)
|
||||
|
||||
.PHONY: all clean dependents
|
||||
.SECONDARY:
|
||||
|
||||
-include ../makefile.targets
|
||||
8
bootloader/Release/objects.mk
Normal file
8
bootloader/Release/objects.mk
Normal file
@ -0,0 +1,8 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
USER_OBJS :=
|
||||
|
||||
LIBS :=
|
||||
|
||||
36
bootloader/Release/sources.mk
Normal file
36
bootloader/Release/sources.mk
Normal file
@ -0,0 +1,36 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
ELF_SRCS :=
|
||||
C_UPPER_SRCS :=
|
||||
CXX_SRCS :=
|
||||
C++_SRCS :=
|
||||
OBJ_SRCS :=
|
||||
CC_SRCS :=
|
||||
ASM_SRCS :=
|
||||
C_SRCS :=
|
||||
CPP_SRCS :=
|
||||
S_UPPER_SRCS :=
|
||||
O_SRCS :=
|
||||
CC_DEPS :=
|
||||
C++_DEPS :=
|
||||
OBJS :=
|
||||
C_UPPER_DEPS :=
|
||||
CXX_DEPS :=
|
||||
SECONDARY_FLASH :=
|
||||
SECONDARY_SIZE :=
|
||||
ASM_DEPS :=
|
||||
S_UPPER_DEPS :=
|
||||
C_DEPS :=
|
||||
CPP_DEPS :=
|
||||
|
||||
# Every subdirectory with source files must be described here
|
||||
SUBDIRS := \
|
||||
src \
|
||||
system/src/cmsis \
|
||||
system/src/cortexm \
|
||||
system/src/diag \
|
||||
system/src/newlib \
|
||||
system/src/stm32f3-stdperiph \
|
||||
|
||||
47
bootloader/Release/src/subdir.mk
Normal file
47
bootloader/Release/src/subdir.mk
Normal file
@ -0,0 +1,47 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../src/_write.c \
|
||||
../src/md5.c
|
||||
|
||||
CPP_SRCS += \
|
||||
../src/DataTerminal.cpp \
|
||||
../src/Timer.cpp \
|
||||
../src/main.cpp
|
||||
|
||||
OBJS += \
|
||||
./src/DataTerminal.o \
|
||||
./src/Timer.o \
|
||||
./src/_write.o \
|
||||
./src/main.o \
|
||||
./src/md5.o
|
||||
|
||||
C_DEPS += \
|
||||
./src/_write.d \
|
||||
./src/md5.d
|
||||
|
||||
CPP_DEPS += \
|
||||
./src/DataTerminal.d \
|
||||
./src/Timer.d \
|
||||
./src/main.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
src/%.o: ../src/%.cpp
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C++ Compiler'
|
||||
arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu++11 -fabi-version=0 -fno-exceptions -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
src/%.o: ../src/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
27
bootloader/Release/system/src/cmsis/subdir.mk
Normal file
27
bootloader/Release/system/src/cmsis/subdir.mk
Normal file
@ -0,0 +1,27 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/cmsis/system_stm32f30x.c \
|
||||
../system/src/cmsis/vectors_stm32f30x.c
|
||||
|
||||
OBJS += \
|
||||
./system/src/cmsis/system_stm32f30x.o \
|
||||
./system/src/cmsis/vectors_stm32f30x.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/cmsis/system_stm32f30x.d \
|
||||
./system/src/cmsis/vectors_stm32f30x.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/cmsis/%.o: ../system/src/cmsis/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
30
bootloader/Release/system/src/cortexm/subdir.mk
Normal file
30
bootloader/Release/system/src/cortexm/subdir.mk
Normal file
@ -0,0 +1,30 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/cortexm/_initialize_hardware.c \
|
||||
../system/src/cortexm/_reset_hardware.c \
|
||||
../system/src/cortexm/exception_handlers.c
|
||||
|
||||
OBJS += \
|
||||
./system/src/cortexm/_initialize_hardware.o \
|
||||
./system/src/cortexm/_reset_hardware.o \
|
||||
./system/src/cortexm/exception_handlers.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/cortexm/_initialize_hardware.d \
|
||||
./system/src/cortexm/_reset_hardware.d \
|
||||
./system/src/cortexm/exception_handlers.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/cortexm/%.o: ../system/src/cortexm/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
27
bootloader/Release/system/src/diag/subdir.mk
Normal file
27
bootloader/Release/system/src/diag/subdir.mk
Normal file
@ -0,0 +1,27 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/diag/Trace.c \
|
||||
../system/src/diag/trace_impl.c
|
||||
|
||||
OBJS += \
|
||||
./system/src/diag/Trace.o \
|
||||
./system/src/diag/trace_impl.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/diag/Trace.d \
|
||||
./system/src/diag/trace_impl.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/diag/%.o: ../system/src/diag/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
57
bootloader/Release/system/src/newlib/subdir.mk
Normal file
57
bootloader/Release/system/src/newlib/subdir.mk
Normal file
@ -0,0 +1,57 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/newlib/_exit.c \
|
||||
../system/src/newlib/_sbrk.c \
|
||||
../system/src/newlib/_startup.c \
|
||||
../system/src/newlib/_syscalls.c \
|
||||
../system/src/newlib/assert.c
|
||||
|
||||
CPP_SRCS += \
|
||||
../system/src/newlib/_cxx.cpp
|
||||
|
||||
OBJS += \
|
||||
./system/src/newlib/_cxx.o \
|
||||
./system/src/newlib/_exit.o \
|
||||
./system/src/newlib/_sbrk.o \
|
||||
./system/src/newlib/_startup.o \
|
||||
./system/src/newlib/_syscalls.o \
|
||||
./system/src/newlib/assert.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/newlib/_exit.d \
|
||||
./system/src/newlib/_sbrk.d \
|
||||
./system/src/newlib/_startup.d \
|
||||
./system/src/newlib/_syscalls.d \
|
||||
./system/src/newlib/assert.d
|
||||
|
||||
CPP_DEPS += \
|
||||
./system/src/newlib/_cxx.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/newlib/%.o: ../system/src/newlib/%.cpp
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C++ Compiler'
|
||||
arm-none-eabi-g++ -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu++11 -fabi-version=0 -fno-exceptions -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
system/src/newlib/%.o: ../system/src/newlib/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
system/src/newlib/_startup.o: ../system/src/newlib/_startup.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -DOS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"system/src/newlib/_startup.d" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
36
bootloader/Release/system/src/stm32f3-stdperiph/subdir.mk
Normal file
36
bootloader/Release/system/src/stm32f3-stdperiph/subdir.mk
Normal file
@ -0,0 +1,36 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
C_SRCS += \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_flash.c \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_gpio.c \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_misc.c \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_rcc.c \
|
||||
../system/src/stm32f3-stdperiph/stm32f30x_usart.c
|
||||
|
||||
OBJS += \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_flash.o \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_gpio.o \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_misc.o \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_rcc.o \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_usart.o
|
||||
|
||||
C_DEPS += \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_flash.d \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_gpio.d \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_misc.d \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_rcc.d \
|
||||
./system/src/stm32f3-stdperiph/stm32f30x_usart.d
|
||||
|
||||
|
||||
# Each subdirectory must supply rules for building sources it contributes
|
||||
system/src/stm32f3-stdperiph/%.o: ../system/src/stm32f3-stdperiph/%.c
|
||||
@echo 'Building file: $<'
|
||||
@echo 'Invoking: Cross ARM C Compiler'
|
||||
arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -ffreestanding -flto -Wall -Wextra -g -DOS_USE_TRACE_SEMIHOSTING_DEBUG -DSTM32F30X -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000 -I"../include" -I"../system/include" -I"../system/include/cmsis" -I"../system/include/stm32f3-stdperiph" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||
@echo 'Finished building: $<'
|
||||
@echo ' '
|
||||
|
||||
|
||||
82
bootloader/include/stm32f30x_conf.h
Normal file
82
bootloader/include/stm32f30x_conf.h
Normal file
@ -0,0 +1,82 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F30x_StdPeriph_Templates/stm32f30x_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-October-2012
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30X_CONF_H
|
||||
#define __STM32F30X_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Comment the line below to disable peripheral header file inclusion */
|
||||
#include "stm32f30x_adc.h"
|
||||
#include "stm32f30x_can.h"
|
||||
#include "stm32f30x_crc.h"
|
||||
#include "stm32f30x_comp.h"
|
||||
#include "stm32f30x_dac.h"
|
||||
#include "stm32f30x_dbgmcu.h"
|
||||
#include "stm32f30x_dma.h"
|
||||
#include "stm32f30x_exti.h"
|
||||
#include "stm32f30x_flash.h"
|
||||
#include "stm32f30x_gpio.h"
|
||||
#include "stm32f30x_syscfg.h"
|
||||
#include "stm32f30x_i2c.h"
|
||||
#include "stm32f30x_iwdg.h"
|
||||
#include "stm32f30x_opamp.h"
|
||||
#include "stm32f30x_pwr.h"
|
||||
#include "stm32f30x_rcc.h"
|
||||
#include "stm32f30x_rtc.h"
|
||||
#include "stm32f30x_spi.h"
|
||||
#include "stm32f30x_tim.h"
|
||||
#include "stm32f30x_usart.h"
|
||||
#include "stm32f30x_wwdg.h"
|
||||
#include "stm32f30x_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function which reports
|
||||
* the name of the source file and the source line number of the call
|
||||
* that failed. If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F30X_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
8
bootloader/ldscripts/libs.ld
Normal file
8
bootloader/ldscripts/libs.ld
Normal file
@ -0,0 +1,8 @@
|
||||
|
||||
/*
|
||||
* Placeholder to list other libraries required by the application.
|
||||
|
||||
GROUP(
|
||||
)
|
||||
|
||||
*/
|
||||
32
bootloader/ldscripts/mem.ld
Normal file
32
bootloader/ldscripts/mem.ld
Normal file
@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Memory Spaces Definitions.
|
||||
*
|
||||
* Need modifying for a specific board.
|
||||
* FLASH.ORIGIN: starting address of flash
|
||||
* FLASH.LENGTH: length of flash
|
||||
* RAM.ORIGIN: starting address of RAM bank 0
|
||||
* RAM.LENGTH: length of RAM bank 0
|
||||
*
|
||||
* The values below can be addressed in further linker scripts
|
||||
* using functions like 'ORIGIN(RAM)' or 'LENGTH(RAM)'.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 40K
|
||||
CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 0K
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0
|
||||
MEMORY_ARRAY (xrw) : ORIGIN = 0x20002000, LENGTH = 0
|
||||
}
|
||||
|
||||
/*
|
||||
* For external ram use something like:
|
||||
|
||||
RAM (xrw) : ORIGIN = 0x64000000, LENGTH = 2048K
|
||||
|
||||
*/
|
||||
445
bootloader/ldscripts/sections.ld
Normal file
445
bootloader/ldscripts/sections.ld
Normal file
@ -0,0 +1,445 @@
|
||||
/*
|
||||
* Default linker script for Cortex-M (it includes specifics for STM32F[34]xx).
|
||||
*
|
||||
* To make use of the multi-region initialisations, define
|
||||
* OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS for the _startup.c file.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The '__stack' definition is required by crt0, do not remove it.
|
||||
*/
|
||||
__stack = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
_estack = __stack; /* STM specific definition */
|
||||
|
||||
/*
|
||||
* Default stack sizes.
|
||||
* These are used by the startup in order to allocate stacks
|
||||
* for the different modes.
|
||||
*/
|
||||
|
||||
__Main_Stack_Size = 1024 ;
|
||||
|
||||
PROVIDE ( _Main_Stack_Size = __Main_Stack_Size ) ;
|
||||
|
||||
__Main_Stack_Limit = __stack - __Main_Stack_Size ;
|
||||
|
||||
/* "PROVIDE" allows to easily override these values from an
|
||||
* object file or the command line. */
|
||||
PROVIDE ( _Main_Stack_Limit = __Main_Stack_Limit ) ;
|
||||
|
||||
/*
|
||||
* There will be a link error if there is not this amount of
|
||||
* RAM free at the end.
|
||||
*/
|
||||
_Minimum_Stack_Size = 256 ;
|
||||
|
||||
/*
|
||||
* Default heap definitions.
|
||||
* The heap start immediately after the last statically allocated
|
||||
* .sbss/.noinit section, and extends up to the main stack limit.
|
||||
*/
|
||||
PROVIDE ( _Heap_Begin = _end_noinit ) ;
|
||||
PROVIDE ( _Heap_Limit = __stack - __Main_Stack_Size ) ;
|
||||
|
||||
/*
|
||||
* The entry point is informative, for debuggers and simulators,
|
||||
* since the Cortex-M vector points to it anyway.
|
||||
*/
|
||||
ENTRY(_start)
|
||||
|
||||
|
||||
/* Sections Definitions */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* For Cortex-M devices, the beginning of the startup code is stored in
|
||||
* the .isr_vector section, which goes to FLASH.
|
||||
*/
|
||||
.isr_vector : ALIGN(4)
|
||||
{
|
||||
FILL(0xFF)
|
||||
|
||||
__vectors_start = ABSOLUTE(.) ;
|
||||
__vectors_start__ = ABSOLUTE(.) ; /* STM specific definition */
|
||||
KEEP(*(.isr_vector)) /* Interrupt vectors */
|
||||
|
||||
KEEP(*(.cfmconfig)) /* Freescale configuration words */
|
||||
|
||||
/*
|
||||
* This section is here for convenience, to store the
|
||||
* startup code at the beginning of the flash area, hoping that
|
||||
* this will increase the readability of the listing.
|
||||
*/
|
||||
*(.after_vectors .after_vectors.*) /* Startup code and ISR */
|
||||
|
||||
} >FLASH
|
||||
|
||||
.inits : ALIGN(4)
|
||||
{
|
||||
/*
|
||||
* Memory regions initialisation arrays.
|
||||
*
|
||||
* Thee are two kinds of arrays for each RAM region, one for
|
||||
* data and one for bss. Each is iterrated at startup and the
|
||||
* region initialisation is performed.
|
||||
*
|
||||
* The data array includes:
|
||||
* - from (LOADADDR())
|
||||
* - region_begin (ADDR())
|
||||
* - region_end (ADDR()+SIZEOF())
|
||||
*
|
||||
* The bss array includes:
|
||||
* - region_begin (ADDR())
|
||||
* - region_end (ADDR()+SIZEOF())
|
||||
*
|
||||
* WARNING: It is mandatory that the regions are word aligned,
|
||||
* since the initialisation code works only on words.
|
||||
*/
|
||||
|
||||
__data_regions_array_start = .;
|
||||
|
||||
LONG(LOADADDR(.data));
|
||||
LONG(ADDR(.data));
|
||||
LONG(ADDR(.data)+SIZEOF(.data));
|
||||
|
||||
LONG(LOADADDR(.data_CCMRAM));
|
||||
LONG(ADDR(.data_CCMRAM));
|
||||
LONG(ADDR(.data_CCMRAM)+SIZEOF(.data_CCMRAM));
|
||||
|
||||
__data_regions_array_end = .;
|
||||
|
||||
__bss_regions_array_start = .;
|
||||
|
||||
LONG(ADDR(.bss));
|
||||
LONG(ADDR(.bss)+SIZEOF(.bss));
|
||||
|
||||
LONG(ADDR(.bss_CCMRAM));
|
||||
LONG(ADDR(.bss_CCMRAM)+SIZEOF(.bss_CCMRAM));
|
||||
|
||||
__bss_regions_array_end = .;
|
||||
|
||||
/* End of memory regions initialisation arrays. */
|
||||
|
||||
/*
|
||||
* These are the old initialisation sections, intended to contain
|
||||
* naked code, with the prologue/epilogue added by crti.o/crtn.o
|
||||
* when linking with startup files. The standalone startup code
|
||||
* currently does not run these, better use the init arrays below.
|
||||
*/
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/*
|
||||
* The preinit code, i.e. an array of pointers to initialisation
|
||||
* functions to be performed before constructors.
|
||||
*/
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
|
||||
/*
|
||||
* Used to run the SystemInit() before anything else.
|
||||
*/
|
||||
KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))
|
||||
|
||||
/*
|
||||
* Used for other platform inits.
|
||||
*/
|
||||
KEEP(*(.preinit_array_platform .preinit_array_platform.*))
|
||||
|
||||
/*
|
||||
* The application inits. If you need to enforce some order in
|
||||
* execution, create new sections, as before.
|
||||
*/
|
||||
KEEP(*(.preinit_array .preinit_array.*))
|
||||
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/*
|
||||
* The init code, i.e. an array of pointers to static constructors.
|
||||
*/
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/*
|
||||
* The fini code, i.e. an array of pointers to static destructors.
|
||||
*/
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
} >FLASH
|
||||
|
||||
/*
|
||||
* For some STRx devices, the beginning of the startup code
|
||||
* is stored in the .flashtext section, which goes to FLASH.
|
||||
*/
|
||||
.flashtext : ALIGN(4)
|
||||
{
|
||||
*(.flashtext .flashtext.*) /* Startup code */
|
||||
} >FLASH
|
||||
|
||||
|
||||
/*
|
||||
* The program code is stored in the .text section,
|
||||
* which goes to FLASH.
|
||||
*/
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
*(.text .text.*) /* all remaining code */
|
||||
|
||||
/* read-only data (constants) */
|
||||
*(.rodata .rodata.* .constdata .constdata.*)
|
||||
|
||||
*(vtable) /* C++ virtual tables */
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
/*
|
||||
* Stub sections generated by the linker, to glue together
|
||||
* ARM and Thumb code. .glue_7 is used for ARM code calling
|
||||
* Thumb code, and .glue_7t is used for Thumb code calling
|
||||
* ARM code. Apparently always generated by the linker, for some
|
||||
* architectures, so better leave them here.
|
||||
*/
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
|
||||
} >FLASH
|
||||
|
||||
/* ARM magic sections */
|
||||
.ARM.extab : ALIGN(4)
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
.ARM.exidx : ALIGN(4)
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
__etext = .;
|
||||
|
||||
/* MEMORY_ARRAY */
|
||||
/*
|
||||
.ROarraySection :
|
||||
{
|
||||
*(.ROarraySection .ROarraySection.*)
|
||||
} >MEMORY_ARRAY
|
||||
*/
|
||||
|
||||
/*
|
||||
* The secondary initialised data section.
|
||||
*/
|
||||
.data_CCMRAM : ALIGN(4)
|
||||
{
|
||||
FILL(0xFF)
|
||||
*(.data.CCMRAM .data.CCMRAM.*)
|
||||
. = ALIGN(4) ;
|
||||
} > CCMRAM AT>FLASH
|
||||
|
||||
/*
|
||||
* This address is used by the startup code to
|
||||
* initialise the .data section.
|
||||
*/
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/*
|
||||
* The initialised data section.
|
||||
*
|
||||
* The program executes knowing that the data is in the RAM
|
||||
* but the loader puts the initial values in the FLASH (inidata).
|
||||
* It is one task of the startup to copy the initial values from
|
||||
* FLASH to RAM.
|
||||
*/
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xFF)
|
||||
/* This is used by the startup code to initialise the .data section */
|
||||
_sdata = . ; /* STM specific definition */
|
||||
__data_start__ = . ;
|
||||
*(.data_begin .data_begin.*)
|
||||
|
||||
*(.data .data.*)
|
||||
|
||||
*(.data_end .data_end.*)
|
||||
. = ALIGN(4);
|
||||
|
||||
/* This is used by the startup code to initialise the .data section */
|
||||
_edata = . ; /* STM specific definition */
|
||||
__data_end__ = . ;
|
||||
|
||||
} >RAM AT>FLASH
|
||||
|
||||
/*
|
||||
* The uninitialised data sections. NOLOAD is used to avoid
|
||||
* the "section `.bss' type changed to PROGBITS" warning
|
||||
*/
|
||||
|
||||
/* The secondary uninitialised data section. */
|
||||
.bss_CCMRAM (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.bss.CCMRAM .bss.CCMRAM.*)
|
||||
} > CCMRAM
|
||||
|
||||
/* The primary uninitialised data section. */
|
||||
.bss (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
__bss_start__ = .; /* standard newlib definition */
|
||||
_sbss = .; /* STM specific definition */
|
||||
*(.bss_begin .bss_begin.*)
|
||||
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
|
||||
*(.bss_end .bss_end.*)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .; /* standard newlib definition */
|
||||
_ebss = . ; /* STM specific definition */
|
||||
} >RAM
|
||||
|
||||
.noinit_CCMRAM (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.CCMRAM .noinit.CCMRAM.*)
|
||||
} > CCMRAM
|
||||
|
||||
.noinit (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
_noinit = .;
|
||||
|
||||
*(.noinit .noinit.*)
|
||||
|
||||
. = ALIGN(4) ;
|
||||
_end_noinit = .;
|
||||
} > RAM
|
||||
|
||||
/* Mandatory to be word aligned, _sbrk assumes this */
|
||||
PROVIDE ( end = _end_noinit ); /* was _ebss */
|
||||
PROVIDE ( _end = _end_noinit );
|
||||
PROVIDE ( __end = _end_noinit );
|
||||
PROVIDE ( __end__ = _end_noinit );
|
||||
|
||||
/*
|
||||
* Used for validation only, do not allocate anything here!
|
||||
*
|
||||
* This is just to check that there is enough RAM left for the Main
|
||||
* stack. It should generate an error if it's full.
|
||||
*/
|
||||
._check_stack : ALIGN(4)
|
||||
{
|
||||
. = . + _Minimum_Stack_Size ;
|
||||
} >RAM
|
||||
|
||||
/*
|
||||
* The FLASH Bank1.
|
||||
* The C or assembly source must explicitly place the code
|
||||
* or data there using the "section" attribute.
|
||||
*/
|
||||
.b1text : ALIGN(4)
|
||||
{
|
||||
*(.b1text) /* remaining code */
|
||||
*(.b1rodata) /* read-only data (constants) */
|
||||
*(.b1rodata.*)
|
||||
} >FLASHB1
|
||||
|
||||
/*
|
||||
* The EXTMEM.
|
||||
* The C or assembly source must explicitly place the code or data there
|
||||
* using the "section" attribute.
|
||||
*/
|
||||
|
||||
/* EXTMEM Bank0 */
|
||||
.eb0text : ALIGN(4)
|
||||
{
|
||||
*(.eb0text) /* remaining code */
|
||||
*(.eb0rodata) /* read-only data (constants) */
|
||||
*(.eb0rodata.*)
|
||||
} >EXTMEMB0
|
||||
|
||||
/* EXTMEM Bank1 */
|
||||
.eb1text : ALIGN(4)
|
||||
{
|
||||
*(.eb1text) /* remaining code */
|
||||
*(.eb1rodata) /* read-only data (constants) */
|
||||
*(.eb1rodata.*)
|
||||
} >EXTMEMB1
|
||||
|
||||
/* EXTMEM Bank2 */
|
||||
.eb2text : ALIGN(4)
|
||||
{
|
||||
*(.eb2text) /* remaining code */
|
||||
*(.eb2rodata) /* read-only data (constants) */
|
||||
*(.eb2rodata.*)
|
||||
} >EXTMEMB2
|
||||
|
||||
/* EXTMEM Bank0 */
|
||||
.eb3text : ALIGN(4)
|
||||
{
|
||||
*(.eb3text) /* remaining code */
|
||||
*(.eb3rodata) /* read-only data (constants) */
|
||||
*(.eb3rodata.*)
|
||||
} >EXTMEMB3
|
||||
|
||||
|
||||
/* After that there are only debugging sections. */
|
||||
|
||||
/* This can remove the debugging information from the standard libraries */
|
||||
/*
|
||||
DISCARD :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
*/
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/*
|
||||
* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0.
|
||||
*/
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
30
bootloader/src/ApplicationMetadata.h
Normal file
30
bootloader/src/ApplicationMetadata.h
Normal file
@ -0,0 +1,30 @@
|
||||
/*
|
||||
* ApplicationMetadata.h
|
||||
*
|
||||
* Created on: Jun 8, 2016
|
||||
* Author: peter
|
||||
*/
|
||||
|
||||
#ifndef APPLICATIONMETADATA_H_
|
||||
#define APPLICATIONMETADATA_H_
|
||||
#include <stm32f30x.h>
|
||||
|
||||
|
||||
|
||||
#define METADATA_ADDRESS 0x08003800
|
||||
#define APPLICATION_ADDRESS 0x08004000
|
||||
#define ISR_VECTOR_OFFSET 0x00004000
|
||||
|
||||
#define METADATA_MAGIC 0x0badf00d
|
||||
#define FLASH_PAGE_SIZE 2048
|
||||
|
||||
typedef struct {
|
||||
uint32_t magic;
|
||||
char revision[8];
|
||||
uint32_t size;
|
||||
uint8_t md5[16];
|
||||
}
|
||||
ApplicationMetadata;
|
||||
|
||||
|
||||
#endif /* APPLICATIONMETADATA_H_ */
|
||||
307
bootloader/src/DataTerminal.cpp
Normal file
307
bootloader/src/DataTerminal.cpp
Normal file
@ -0,0 +1,307 @@
|
||||
/*
|
||||
* Terminal.cpp
|
||||
*
|
||||
* Created on: Apr 19, 2016
|
||||
* Author: peter
|
||||
*/
|
||||
|
||||
#include "DataTerminal.hpp"
|
||||
|
||||
#include "stm32f30x.h"
|
||||
#include <stdio.h>
|
||||
#include <cstring>
|
||||
#include <diag/Trace.h>
|
||||
#include <cassert>
|
||||
|
||||
|
||||
//#define DRY_RUN
|
||||
|
||||
|
||||
DataTerminal &DataTerminal::instance()
|
||||
{
|
||||
static DataTerminal __instance;
|
||||
return __instance;
|
||||
}
|
||||
|
||||
void DataTerminal::init()
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
NVIC_InitTypeDef NVIC_InitStruct;
|
||||
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); // For USART2
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_7);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_7);
|
||||
|
||||
// Initialize pins as alternative function 7 (USART)
|
||||
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStruct.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_Level_1;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
// These two pins are LEDs. Just turn them on to indicate we have entered "update" mode.
|
||||
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_14 | GPIO_Pin_15;
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
//GPIO_SetBits(GPIOB, GPIO_Pin_14);
|
||||
//GPIO_SetBits(GPIOB, GPIO_Pin_15);
|
||||
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||
|
||||
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
USART_StructInit(&USART_InitStructure);
|
||||
|
||||
USART_InitStructure.USART_BaudRate = 38400;
|
||||
USART_Init(USART2, &USART_InitStructure);
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
|
||||
USART_Cmd(USART2, ENABLE);
|
||||
|
||||
USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
|
||||
NVIC_InitStruct.NVIC_IRQChannel = USART2_IRQn;
|
||||
NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
|
||||
NVIC_Init(&NVIC_InitStruct);
|
||||
|
||||
//write("[SYSTEM][Waiting for transfer]\r\n");
|
||||
}
|
||||
|
||||
DataTerminal::DataTerminal()
|
||||
: mState(STATE_WAITING), mByteCount(0), mWriteAddress(0)
|
||||
{
|
||||
assert(APPLICATION_ADDRESS%FLASH_PAGE_SIZE == 0);
|
||||
assert(METADATA_ADDRESS%FLASH_PAGE_SIZE == 0);
|
||||
assert(sizeof mMetadata % 4 == 0);
|
||||
memset(mCurrPage, 0, sizeof mCurrPage);
|
||||
}
|
||||
|
||||
void printmd5(uint8_t *d)
|
||||
{
|
||||
char m[35];
|
||||
for ( size_t i = 0; i < 16; ++i ) {
|
||||
sprintf(m + i*2, "%.2x", d[i]);
|
||||
}
|
||||
trace_printf("%s\n",m);
|
||||
}
|
||||
|
||||
void DataTerminal::processByte(uint8_t byte)
|
||||
{
|
||||
switch(mState) {
|
||||
case STATE_WAITING:
|
||||
if ( byte == START_TRANSFER_CMD ) {
|
||||
mState = STATE_IN_TRANSFER_HEADER;
|
||||
mByteCount = 0;
|
||||
trace_printf("Receiving metadata\n");
|
||||
GPIO_SetBits(GPIOB, GPIO_Pin_14);
|
||||
writeCmd(ACK);
|
||||
}
|
||||
else {
|
||||
trace_printf("Bad command: %.2x\n", byte);
|
||||
fail();
|
||||
}
|
||||
break;
|
||||
case STATE_IN_TRANSFER_HEADER: {
|
||||
//trace_printf("1 byte\n");
|
||||
char *p = (char*)&mMetadata;
|
||||
memcpy(p + mByteCount, &byte, 1);
|
||||
++mByteCount;
|
||||
if ( mByteCount == sizeof mMetadata ) {
|
||||
trace_printf("Magick: %.8x\n", mMetadata.magic);
|
||||
// Is the metadata sane?
|
||||
if ( mMetadata.magic == METADATA_MAGIC ) {
|
||||
mState = STATE_IN_TRANSFER_BLOCK;
|
||||
trace_printf("Expecting %d bytes\n", mMetadata.size);
|
||||
printmd5(mMetadata.md5);
|
||||
GPIO_SetBits(GPIOB, GPIO_Pin_14);
|
||||
mByteCount = 0;
|
||||
mWriteAddress = APPLICATION_ADDRESS;
|
||||
MD5Init(&mMD5);
|
||||
unlockFlash();
|
||||
writeCmd(ACK);
|
||||
}
|
||||
else {
|
||||
trace_printf("Bad metadata \n");
|
||||
fail();
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case STATE_IN_TRANSFER_BLOCK:
|
||||
MD5Update(&mMD5, &byte, 1);
|
||||
if ( mByteCount == 0 ) {
|
||||
GPIO_SetBits(GPIOB, GPIO_Pin_15);
|
||||
}
|
||||
|
||||
size_t offset = mByteCount % FLASH_PAGE_SIZE;
|
||||
assert(offset < sizeof mCurrPage);
|
||||
memcpy(mCurrPage + offset, &byte, 1);
|
||||
|
||||
++mByteCount;
|
||||
|
||||
if ( mByteCount % FLASH_PAGE_SIZE == 0 ) {
|
||||
flushPage();
|
||||
}
|
||||
|
||||
// Acknowledge every 1K
|
||||
if ( mByteCount % 1024 == 0 ) {
|
||||
trace_printf("Sending ACK\n");
|
||||
writeCmd(ACK);
|
||||
}
|
||||
|
||||
|
||||
if ( mByteCount == mMetadata.size ) {
|
||||
if ( mMetadata.size % 1024 ) {
|
||||
// We have a partial page to write
|
||||
flushPage();
|
||||
writeCmd(ACK);
|
||||
}
|
||||
|
||||
// Last byte!
|
||||
trace_printf("Received %d bytes\n", mMetadata.size);
|
||||
GPIO_ResetBits(GPIOB, GPIO_Pin_14);
|
||||
mState = STATE_WAITING;
|
||||
|
||||
uint8_t d[16];
|
||||
MD5Final(d, &mMD5);
|
||||
printmd5(d);
|
||||
if ( memcmp(d, mMetadata.md5, 16) ) {
|
||||
// Bad MD5
|
||||
trace_printf("MD5 mismatch :( \n");
|
||||
fail();
|
||||
}
|
||||
else {
|
||||
// Good transfer
|
||||
trace_printf("MD5 match :) \n");
|
||||
writeCmd(ACK);
|
||||
|
||||
|
||||
flushMetadata();
|
||||
lockFlash();
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void DataTerminal::fail()
|
||||
{
|
||||
mByteCount = 0;
|
||||
mState = STATE_WAITING;
|
||||
GPIO_ResetBits(GPIOB, GPIO_Pin_14|GPIO_Pin_15);
|
||||
FLASH_Lock();
|
||||
writeCmd(NACK);
|
||||
}
|
||||
|
||||
void DataTerminal::unlockFlash()
|
||||
{
|
||||
#ifdef DRY_RUN
|
||||
trace_printf("Mock flash unlock\n");
|
||||
#else
|
||||
FLASH_Unlock();
|
||||
FLASH_WaitForLastOperation(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void DataTerminal::lockFlash()
|
||||
{
|
||||
#ifdef DRY_RUN
|
||||
trace_printf("Mock flash lock\n");
|
||||
#else
|
||||
FLASH_Lock();
|
||||
FLASH_WaitForLastOperation(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void DataTerminal::flushPage()
|
||||
{
|
||||
#ifdef DRY_RUN
|
||||
trace_printf("Mock write for flash page at %.8x\n", mWriteAddress);
|
||||
mWriteAddress += FLASH_PAGE_SIZE;
|
||||
#else
|
||||
trace_printf("Writing Flash page at %.8x\n", mWriteAddress);
|
||||
FLASH_ErasePage(mWriteAddress);
|
||||
FLASH_WaitForLastOperation(0);
|
||||
char *p = mCurrPage;
|
||||
for ( size_t i = 0; i < FLASH_PAGE_SIZE; i += 4, p += 4) {
|
||||
FLASH_ProgramWord(mWriteAddress + i, *(uint32_t*)p);
|
||||
FLASH_WaitForLastOperation(0);
|
||||
}
|
||||
|
||||
trace_printf("Wrote Flash page at %.8x\n", mWriteAddress);
|
||||
mWriteAddress += FLASH_PAGE_SIZE;
|
||||
memset(mCurrPage, 0, sizeof mCurrPage);
|
||||
#endif
|
||||
}
|
||||
|
||||
void DataTerminal::flushMetadata()
|
||||
{
|
||||
#ifdef DRY_RUN
|
||||
trace_printf("Mock write for metadata page at %.8x\n", METADATA_ADDRESS);
|
||||
#else
|
||||
FLASH_ErasePage(METADATA_ADDRESS);
|
||||
FLASH_WaitForLastOperation(0);
|
||||
char *p = (char*)&mMetadata;
|
||||
for ( size_t i = 0; i < sizeof mMetadata; i += 4, p += 4 ) {
|
||||
FLASH_ProgramWord(METADATA_ADDRESS + i, *(uint32_t*)p);
|
||||
FLASH_WaitForLastOperation(0);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void write_char(USART_TypeDef* USARTx, char c)
|
||||
{
|
||||
while (!(USARTx->ISR & 0x00000040))
|
||||
;
|
||||
|
||||
USART_SendData(USARTx, c);
|
||||
}
|
||||
|
||||
void DataTerminal::write(const char* s)
|
||||
{
|
||||
for ( int i = 0; s[i] != 0; ++i )
|
||||
write_char(USART2, s[i]);
|
||||
}
|
||||
|
||||
void DataTerminal::writeCmd(uint8_t cmd)
|
||||
{
|
||||
write_char(USART2, (char)cmd);
|
||||
}
|
||||
|
||||
void DataTerminal::clearScreen()
|
||||
{
|
||||
_write("\033[2J");
|
||||
_write("\033[H");
|
||||
}
|
||||
|
||||
void DataTerminal::_write(const char *s)
|
||||
{
|
||||
write(s);
|
||||
}
|
||||
|
||||
|
||||
extern "C" {
|
||||
|
||||
void USART2_IRQHandler(void)
|
||||
{
|
||||
if ( USART_GetITStatus(USART2, USART_IT_RXNE) ) {
|
||||
uint8_t byte = (uint8_t)USART2->RDR;
|
||||
DataTerminal::instance().processByte(byte);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
61
bootloader/src/DataTerminal.hpp
Normal file
61
bootloader/src/DataTerminal.hpp
Normal file
@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Terminal.hpp
|
||||
*
|
||||
* Created on: Apr 19, 2016
|
||||
* Author: peter
|
||||
*/
|
||||
|
||||
#ifndef DATATERMINAL_HPP_
|
||||
#define DATATERMINAL_HPP_
|
||||
|
||||
#include <inttypes.h>
|
||||
#include "ApplicationMetadata.h"
|
||||
#include "md5.h"
|
||||
|
||||
|
||||
typedef enum {
|
||||
STATE_WAITING = 0,
|
||||
STATE_IN_TRANSFER_HEADER,
|
||||
STATE_IN_TRANSFER_BLOCK
|
||||
}
|
||||
TerminalState;
|
||||
|
||||
#define ACK (uint8_t)0x00
|
||||
#define NACK (uint8_t)0x01
|
||||
|
||||
#define START_TRANSFER_CMD 0xd4
|
||||
#define START_BLOCK_CMD 0xd6
|
||||
|
||||
|
||||
class DataTerminal
|
||||
{
|
||||
public:
|
||||
static DataTerminal &instance();
|
||||
|
||||
void init();
|
||||
|
||||
void write(const char* line);
|
||||
void processByte(uint8_t b);
|
||||
void clearScreen();
|
||||
private:
|
||||
DataTerminal();
|
||||
|
||||
void _write(const char* s);
|
||||
void writeCmd(uint8_t cmd);
|
||||
void fail();
|
||||
void flushPage();
|
||||
void flushMetadata();
|
||||
void unlockFlash();
|
||||
void lockFlash();
|
||||
private:
|
||||
TerminalState mState;
|
||||
uint32_t mByteCount;
|
||||
ApplicationMetadata mMetadata;
|
||||
MD5_CTX mMD5;
|
||||
char mCurrPage[FLASH_PAGE_SIZE];
|
||||
uint32_t mWriteAddress;
|
||||
};
|
||||
|
||||
|
||||
|
||||
#endif /* DATATERMINAL_HPP_ */
|
||||
42
bootloader/src/Timer.cpp
Normal file
42
bootloader/src/Timer.cpp
Normal file
@ -0,0 +1,42 @@
|
||||
//
|
||||
// This file is part of the GNU ARM Eclipse distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
#include "Timer.h"
|
||||
#include "cortexm/ExceptionHandlers.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(USE_HAL_DRIVER)
|
||||
extern "C" void HAL_IncTick(void);
|
||||
#endif
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
volatile Timer::ticks_t Timer::ms_delayCount;
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
void
|
||||
Timer::sleep(ticks_t ticks)
|
||||
{
|
||||
ms_delayCount = ticks;
|
||||
|
||||
// Busy wait until the SysTick decrements the counter to zero.
|
||||
while (ms_delayCount != 0u)
|
||||
;
|
||||
}
|
||||
|
||||
// ----- SysTick_Handler() ----------------------------------------------------
|
||||
|
||||
extern "C" void
|
||||
SysTick_Handler(void)
|
||||
{
|
||||
#if defined(USE_HAL_DRIVER)
|
||||
HAL_IncTick();
|
||||
#endif
|
||||
Timer::tick();
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
49
bootloader/src/Timer.h
Normal file
49
bootloader/src/Timer.h
Normal file
@ -0,0 +1,49 @@
|
||||
//
|
||||
// This file is part of the GNU ARM Eclipse distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
#ifndef TIMER_H_
|
||||
#define TIMER_H_
|
||||
|
||||
#include "cmsis_device.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
class Timer
|
||||
{
|
||||
public:
|
||||
typedef uint32_t ticks_t;
|
||||
static constexpr ticks_t FREQUENCY_HZ = 1000u;
|
||||
|
||||
private:
|
||||
static volatile ticks_t ms_delayCount;
|
||||
|
||||
public:
|
||||
// Default constructor
|
||||
Timer() = default;
|
||||
|
||||
inline void
|
||||
start(void)
|
||||
{
|
||||
// Use SysTick as reference for the delay loops.
|
||||
SysTick_Config(SystemCoreClock / FREQUENCY_HZ);
|
||||
}
|
||||
|
||||
static void
|
||||
sleep(ticks_t ticks);
|
||||
|
||||
inline static void
|
||||
tick(void)
|
||||
{
|
||||
// Decrement to zero the counter used by the delay routine.
|
||||
if (ms_delayCount != 0u)
|
||||
{
|
||||
--ms_delayCount;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#endif // TIMER_H_
|
||||
50
bootloader/src/_write.c
Normal file
50
bootloader/src/_write.c
Normal file
@ -0,0 +1,50 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// Do not include on semihosting and when freestanding
|
||||
#if !defined(OS_USE_SEMIHOSTING) && !(__STDC_HOSTED__ == 0)
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include <errno.h>
|
||||
#include "diag/Trace.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// When using retargetted configurations, the standard write() system call,
|
||||
// after a long way inside newlib, finally calls this implementation function.
|
||||
|
||||
// Based on the file descriptor, it can send arrays of characters to
|
||||
// different physical devices.
|
||||
|
||||
// Currently only the output and error file descriptors are tested,
|
||||
// and the characters are forwarded to the trace device, mainly
|
||||
// for demonstration purposes. Adjust it for your specific needs.
|
||||
|
||||
// For freestanding applications this file is not used and can be safely
|
||||
// ignored.
|
||||
|
||||
ssize_t
|
||||
_write (int fd, const char* buf, size_t nbyte);
|
||||
|
||||
ssize_t
|
||||
_write (int fd __attribute__((unused)), const char* buf __attribute__((unused)),
|
||||
size_t nbyte __attribute__((unused)))
|
||||
{
|
||||
#if defined(TRACE)
|
||||
// STDOUT and STDERR are routed to the trace device
|
||||
if (fd == 1 || fd == 2)
|
||||
{
|
||||
return trace_write (buf, nbyte);
|
||||
}
|
||||
#endif // TRACE
|
||||
|
||||
errno = ENOSYS;
|
||||
return -1;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#endif // !defined(OS_USE_SEMIHOSTING) && !(__STDC_HOSTED__ == 0)
|
||||
142
bootloader/src/main.cpp
Normal file
142
bootloader/src/main.cpp
Normal file
@ -0,0 +1,142 @@
|
||||
//
|
||||
// This file is part of the GNU ARM Eclipse distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "diag/Trace.h"
|
||||
#include <stm32f30x.h>
|
||||
#include "md5.h"
|
||||
#include <cstring>
|
||||
#include "ApplicationMetadata.h"
|
||||
#include "DataTerminal.hpp"
|
||||
#include "Timer.h"
|
||||
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
//
|
||||
// Standalone STM32F3 empty sample (trace via DEBUG).
|
||||
//
|
||||
// Trace support is enabled by adding the TRACE macro definition.
|
||||
// By default the trace messages are forwarded to the DEBUG output,
|
||||
// but can be rerouted to any device or completely suppressed, by
|
||||
// changing the definitions required in system/src/diag/trace_impl.c
|
||||
// (currently OS_USE_TRACE_ITM, OS_USE_TRACE_SEMIHOSTING_DEBUG/_STDOUT).
|
||||
//
|
||||
|
||||
// ----- main() ---------------------------------------------------------------
|
||||
|
||||
// Sample pragmas to cope with warnings. Please note the related line at
|
||||
// the end of this function, used to pop the compiler diagnostics status.
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wunused-parameter"
|
||||
#pragma GCC diagnostic ignored "-Wmissing-declarations"
|
||||
#pragma GCC diagnostic ignored "-Wreturn-type"
|
||||
|
||||
typedef void (*pFunction)(void);
|
||||
|
||||
pFunction JumpToApplication;
|
||||
uint32_t JumpAddress;
|
||||
|
||||
void jump();
|
||||
void enterUARTMode();
|
||||
bool verifyApplicationChecksum(const ApplicationMetadata &metadata);
|
||||
|
||||
Timer __timer;
|
||||
|
||||
void erase()
|
||||
{
|
||||
FLASH_Unlock();
|
||||
FLASH_WaitForLastOperation(0);
|
||||
FLASH_ErasePage(METADATA_ADDRESS);
|
||||
FLASH_WaitForLastOperation(0);
|
||||
FLASH_Lock();
|
||||
FLASH_WaitForLastOperation(0);
|
||||
|
||||
}
|
||||
|
||||
int
|
||||
main(int argc, char* argv[])
|
||||
{
|
||||
//erase();
|
||||
/*
|
||||
* - Read page at METADATA_ADDRESS, look for software metadata
|
||||
* - If no metadata is present, enter UART interactive mode and wait for software upload
|
||||
* - If metadata is present, jump to software start address (APPLICATION_ADDRESS)
|
||||
*/
|
||||
#if 1
|
||||
ApplicationMetadata *metadata = (ApplicationMetadata*)METADATA_ADDRESS;
|
||||
if ( metadata == NULL || metadata->magic != METADATA_MAGIC ) {
|
||||
trace_printf("There is no software installed. Entering UART mode\n");
|
||||
enterUARTMode();
|
||||
|
||||
}
|
||||
else {
|
||||
if ( !verifyApplicationChecksum(*metadata) ) {
|
||||
trace_printf("The software is corrupt. Entering UART mode\n");
|
||||
enterUARTMode();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
trace_printf("Found software rev. %s\n", metadata->revision);
|
||||
#endif
|
||||
|
||||
pFunction start = (pFunction)(*(__IO uint32_t*) (APPLICATION_ADDRESS + 4));
|
||||
trace_printf("Application address: 0x%.8x\n", APPLICATION_ADDRESS);
|
||||
trace_printf("Jump address: 0x%.8x\n", start);
|
||||
|
||||
__timer.start();
|
||||
|
||||
Timer::sleep(2000);
|
||||
|
||||
jump();
|
||||
//while(1);
|
||||
}
|
||||
|
||||
void jump()
|
||||
{
|
||||
/// Initialize user application's Stack Pointer
|
||||
__set_MSP(*(__IO uint32_t*) APPLICATION_ADDRESS);
|
||||
|
||||
/// Reset interrupt vector to application
|
||||
NVIC_SetVectorTable(NVIC_VectTab_FLASH, ISR_VECTOR_OFFSET);
|
||||
|
||||
// Start the application
|
||||
pFunction start = (pFunction)(*(__IO uint32_t*) (APPLICATION_ADDRESS + 4));
|
||||
start();
|
||||
//while(1);
|
||||
}
|
||||
|
||||
void enterUARTMode()
|
||||
{
|
||||
DataTerminal::instance().init();
|
||||
|
||||
// Infinite loop
|
||||
while (1) {
|
||||
// Add your code here.
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
bool verifyApplicationChecksum(const ApplicationMetadata &metadata)
|
||||
{
|
||||
uint8_t hash[16];
|
||||
uint8_t *p = (uint8_t*)APPLICATION_ADDRESS;
|
||||
MD5_CTX ctx;
|
||||
MD5Init(&ctx);
|
||||
for ( uint32_t i = 0; i < metadata.size; ++i, ++p )
|
||||
MD5Update(&ctx, p, 1);
|
||||
|
||||
MD5Final(hash, &ctx);
|
||||
|
||||
return memcmp(hash, metadata.md5, sizeof hash) == 0;
|
||||
}
|
||||
|
||||
|
||||
#pragma GCC diagnostic pop
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
309
bootloader/src/md5.c
Normal file
309
bootloader/src/md5.c
Normal file
@ -0,0 +1,309 @@
|
||||
/*
|
||||
***********************************************************************
|
||||
** md5.c -- the source code for MD5 routines **
|
||||
** RSA Data Security, Inc. MD5 Message-Digest Algorithm **
|
||||
** Created: 2/17/90 RLR **
|
||||
** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **
|
||||
***********************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
***********************************************************************
|
||||
** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. **
|
||||
** **
|
||||
** License to copy and use this software is granted provided that **
|
||||
** it is identified as the "RSA Data Security, Inc. MD5 Message- **
|
||||
** Digest Algorithm" in all material mentioning or referencing this **
|
||||
** software or this function. **
|
||||
** **
|
||||
** License is also granted to make and use derivative works **
|
||||
** provided that such works are identified as "derived from the RSA **
|
||||
** Data Security, Inc. MD5 Message-Digest Algorithm" in all **
|
||||
** material mentioning or referencing the derived work. **
|
||||
** **
|
||||
** RSA Data Security, Inc. makes no representations concerning **
|
||||
** either the merchantability of this software or the suitability **
|
||||
** of this software for any particular purpose. It is provided "as **
|
||||
** is" without express or implied warranty of any kind. **
|
||||
** **
|
||||
** These notices must be retained in any copies of any part of this **
|
||||
** documentation and/or software. **
|
||||
***********************************************************************
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include "md5.h"
|
||||
#include <string.h>
|
||||
|
||||
/*
|
||||
***********************************************************************
|
||||
** Message-digest routines: **
|
||||
** To form the message digest for a message M **
|
||||
** (1) Initialize a context buffer mdContext using MD5Init **
|
||||
** (2) Call MD5Update on mdContext and M **
|
||||
** (3) Call MD5Final on mdContext **
|
||||
** The message digest is now in mdContext->digest[0...15] **
|
||||
***********************************************************************
|
||||
*/
|
||||
|
||||
/* forward declaration */
|
||||
static void Transform (uint32_t *buf, uint32_t *in);
|
||||
|
||||
static unsigned char PADDING[64] = {
|
||||
0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* F, G, H and I are basic MD5 functions */
|
||||
#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
|
||||
#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
|
||||
#define H(x, y, z) ((x) ^ (y) ^ (z))
|
||||
#define I(x, y, z) ((y) ^ ((x) | (~z)))
|
||||
|
||||
/* ROTATE_LEFT rotates x left n bits */
|
||||
#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
|
||||
|
||||
/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */
|
||||
/* Rotation is separate from addition to prevent recomputation */
|
||||
#define FF(a, b, c, d, x, s, ac) \
|
||||
{(a) += F ((b), (c), (d)) + (x) + (uint32_t)(ac); \
|
||||
(a) = ROTATE_LEFT ((a), (s)); \
|
||||
(a) += (b); \
|
||||
}
|
||||
#define GG(a, b, c, d, x, s, ac) \
|
||||
{(a) += G ((b), (c), (d)) + (x) + (uint32_t)(ac); \
|
||||
(a) = ROTATE_LEFT ((a), (s)); \
|
||||
(a) += (b); \
|
||||
}
|
||||
#define HH(a, b, c, d, x, s, ac) \
|
||||
{(a) += H ((b), (c), (d)) + (x) + (uint32_t)(ac); \
|
||||
(a) = ROTATE_LEFT ((a), (s)); \
|
||||
(a) += (b); \
|
||||
}
|
||||
#define II(a, b, c, d, x, s, ac) \
|
||||
{(a) += I ((b), (c), (d)) + (x) + (uint32_t)(ac); \
|
||||
(a) = ROTATE_LEFT ((a), (s)); \
|
||||
(a) += (b); \
|
||||
}
|
||||
|
||||
#ifdef __STDC__
|
||||
#define UL(x) x##UL
|
||||
#else
|
||||
#ifdef WIN32
|
||||
#define UL(x) x##UL
|
||||
#else
|
||||
#define UL(x) x
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* The routine MD5Init initializes the message-digest context
|
||||
mdContext. All fields are set to zero.
|
||||
*/
|
||||
void
|
||||
MD5Init (MD5_CTX *mdContext)
|
||||
{
|
||||
mdContext->i[0] = mdContext->i[1] = (uint32_t)0;
|
||||
|
||||
/* Load magic initialization constants. */
|
||||
mdContext->buf[0] = (uint32_t)0x67452301UL;
|
||||
mdContext->buf[1] = (uint32_t)0xefcdab89UL;
|
||||
mdContext->buf[2] = (uint32_t)0x98badcfeUL;
|
||||
mdContext->buf[3] = (uint32_t)0x10325476UL;
|
||||
}
|
||||
|
||||
/* The routine MD5Update updates the message-digest context to
|
||||
account for the presence of each of the characters inBuf[0..inLen-1]
|
||||
in the message whose digest is being computed.
|
||||
*/
|
||||
void
|
||||
MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen)
|
||||
{
|
||||
uint32_t in[16];
|
||||
int mdi;
|
||||
unsigned int i, ii;
|
||||
|
||||
#if 0
|
||||
ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf);
|
||||
ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf);
|
||||
#endif
|
||||
|
||||
/* compute number of bytes mod 64 */
|
||||
mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
|
||||
|
||||
/* update number of bits */
|
||||
if ((mdContext->i[0] + ((uint32_t)inLen << 3)) < mdContext->i[0]) {
|
||||
mdContext->i[1]++;
|
||||
}
|
||||
mdContext->i[0] += ((uint32_t)inLen << 3);
|
||||
mdContext->i[1] += ((uint32_t)inLen >> 29);
|
||||
|
||||
while (inLen--) {
|
||||
/* add new character to buffer, increment mdi */
|
||||
mdContext->in[mdi++] = *inBuf++;
|
||||
|
||||
/* transform if necessary */
|
||||
if (mdi == 0x40) {
|
||||
for (i = 0, ii = 0; i < 16; i++, ii += 4) {
|
||||
in[i] = (((uint32_t)mdContext->in[ii+3]) << 24) |
|
||||
(((uint32_t)mdContext->in[ii+2]) << 16) |
|
||||
(((uint32_t)mdContext->in[ii+1]) << 8) |
|
||||
((uint32_t)mdContext->in[ii]);
|
||||
}
|
||||
Transform (mdContext->buf, in);
|
||||
mdi = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* The routine MD5Final terminates the message-digest computation and
|
||||
ends with the desired message digest in mdContext->digest[0...15].
|
||||
*/
|
||||
void
|
||||
MD5Final (unsigned char hash[], MD5_CTX *mdContext)
|
||||
{
|
||||
uint32_t in[16];
|
||||
int mdi;
|
||||
unsigned int i, ii;
|
||||
unsigned int padLen;
|
||||
|
||||
/* save number of bits */
|
||||
in[14] = mdContext->i[0];
|
||||
in[15] = mdContext->i[1];
|
||||
|
||||
/* compute number of bytes mod 64 */
|
||||
mdi = (int)((mdContext->i[0] >> 3) & 0x3F);
|
||||
|
||||
/* pad out to 56 mod 64 */
|
||||
padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);
|
||||
MD5Update (mdContext, PADDING, padLen);
|
||||
|
||||
/* append length in bits and transform */
|
||||
for (i = 0, ii = 0; i < 14; i++, ii += 4) {
|
||||
in[i] = (((uint32_t)mdContext->in[ii+3]) << 24) |
|
||||
(((uint32_t)mdContext->in[ii+2]) << 16) |
|
||||
(((uint32_t)mdContext->in[ii+1]) << 8) |
|
||||
((uint32_t)mdContext->in[ii]);
|
||||
}
|
||||
Transform (mdContext->buf, in);
|
||||
|
||||
/* store buffer in digest */
|
||||
for (i = 0, ii = 0; i < 4; i++, ii += 4) {
|
||||
mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF);
|
||||
mdContext->digest[ii+1] =
|
||||
(unsigned char)((mdContext->buf[i] >> 8) & 0xFF);
|
||||
mdContext->digest[ii+2] =
|
||||
(unsigned char)((mdContext->buf[i] >> 16) & 0xFF);
|
||||
mdContext->digest[ii+3] =
|
||||
(unsigned char)((mdContext->buf[i] >> 24) & 0xFF);
|
||||
}
|
||||
memcpy(hash, mdContext->digest, 16);
|
||||
}
|
||||
|
||||
/* Basic MD5 step. Transforms buf based on in.
|
||||
*/
|
||||
static void
|
||||
Transform (uint32_t *buf, uint32_t *in)
|
||||
{
|
||||
uint32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3];
|
||||
|
||||
/* Round 1 */
|
||||
#define S11 7
|
||||
#define S12 12
|
||||
#define S13 17
|
||||
#define S14 22
|
||||
FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
|
||||
FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
|
||||
FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
|
||||
FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
|
||||
FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
|
||||
FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
|
||||
FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
|
||||
FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
|
||||
FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
|
||||
FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
|
||||
FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
|
||||
FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
|
||||
FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
|
||||
FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
|
||||
FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
|
||||
FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
|
||||
|
||||
/* Round 2 */
|
||||
#define S21 5
|
||||
#define S22 9
|
||||
#define S23 14
|
||||
#define S24 20
|
||||
GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
|
||||
GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
|
||||
GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
|
||||
GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
|
||||
GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
|
||||
GG ( d, a, b, c, in[10], S22, UL( 38016083)); /* 22 */
|
||||
GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
|
||||
GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
|
||||
GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
|
||||
GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
|
||||
GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
|
||||
GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
|
||||
GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
|
||||
GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
|
||||
GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
|
||||
GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
|
||||
|
||||
/* Round 3 */
|
||||
#define S31 4
|
||||
#define S32 11
|
||||
#define S33 16
|
||||
#define S34 23
|
||||
HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
|
||||
HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
|
||||
HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
|
||||
HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
|
||||
HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
|
||||
HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
|
||||
HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
|
||||
HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
|
||||
HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
|
||||
HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
|
||||
HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
|
||||
HH ( b, c, d, a, in[ 6], S34, UL( 76029189)); /* 44 */
|
||||
HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
|
||||
HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
|
||||
HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
|
||||
HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
|
||||
|
||||
/* Round 4 */
|
||||
#define S41 6
|
||||
#define S42 10
|
||||
#define S43 15
|
||||
#define S44 21
|
||||
II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
|
||||
II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
|
||||
II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
|
||||
II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
|
||||
II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
|
||||
II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
|
||||
II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
|
||||
II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
|
||||
II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
|
||||
II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
|
||||
II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
|
||||
II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
|
||||
II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
|
||||
II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
|
||||
II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
|
||||
II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
|
||||
|
||||
buf[0] += a;
|
||||
buf[1] += b;
|
||||
buf[2] += c;
|
||||
buf[3] += d;
|
||||
}
|
||||
|
||||
65
bootloader/src/md5.h
Normal file
65
bootloader/src/md5.h
Normal file
@ -0,0 +1,65 @@
|
||||
/*
|
||||
***********************************************************************
|
||||
** md5.h -- header file for implementation of MD5 **
|
||||
** RSA Data Security, Inc. MD5 Message-Digest Algorithm **
|
||||
** Created: 2/17/90 RLR **
|
||||
** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version **
|
||||
** Revised (for MD5): RLR 4/27/91 **
|
||||
** -- G modified to have y&~z instead of y&z **
|
||||
** -- FF, GG, HH modified to add in last register done **
|
||||
** -- Access pattern: round 2 works mod 5, round 3 works mod 3 **
|
||||
** -- distinct additive constant for each step **
|
||||
** -- round 4 added, working mod 7 **
|
||||
***********************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
***********************************************************************
|
||||
** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. **
|
||||
** **
|
||||
** License to copy and use this software is granted provided that **
|
||||
** it is identified as the "RSA Data Security, Inc. MD5 Message- **
|
||||
** Digest Algorithm" in all material mentioning or referencing this **
|
||||
** software or this function. **
|
||||
** **
|
||||
** License is also granted to make and use derivative works **
|
||||
** provided that such works are identified as "derived from the RSA **
|
||||
** Data Security, Inc. MD5 Message-Digest Algorithm" in all **
|
||||
** material mentioning or referencing the derived work. **
|
||||
** **
|
||||
** RSA Data Security, Inc. makes no representations concerning **
|
||||
** either the merchantability of this software or the suitability **
|
||||
** of this software for any particular purpose. It is provided "as **
|
||||
** is" without express or implied warranty of any kind. **
|
||||
** **
|
||||
** These notices must be retained in any copies of any part of this **
|
||||
** documentation and/or software. **
|
||||
***********************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MD5_H
|
||||
#define MD5_H
|
||||
|
||||
#include <inttypes.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Data structure for MD5 (Message-Digest) computation */
|
||||
typedef struct {
|
||||
uint32_t i[2]; /* number of _bits_ handled mod 2^64 */
|
||||
uint32_t buf[4]; /* scratch buffer */
|
||||
unsigned char in[64]; /* input buffer */
|
||||
unsigned char digest[16]; /* actual digest after MD5Final call */
|
||||
} MD5_CTX;
|
||||
|
||||
void MD5Init ( MD5_CTX *mdContext);
|
||||
void MD5Update( MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen);
|
||||
void MD5Final ( unsigned char hash[], MD5_CTX *mdContext);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MD5_H */
|
||||
120
bootloader/system/include/arm/semihosting.h
Normal file
120
bootloader/system/include/arm/semihosting.h
Normal file
@ -0,0 +1,120 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
#ifndef ARM_SEMIHOSTING_H_
|
||||
#define ARM_SEMIHOSTING_H_
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// Semihosting operations.
|
||||
enum OperationNumber
|
||||
{
|
||||
// Regular operations
|
||||
SEMIHOSTING_EnterSVC = 0x17,
|
||||
SEMIHOSTING_ReportException = 0x18,
|
||||
SEMIHOSTING_SYS_CLOSE = 0x02,
|
||||
SEMIHOSTING_SYS_CLOCK = 0x10,
|
||||
SEMIHOSTING_SYS_ELAPSED = 0x30,
|
||||
SEMIHOSTING_SYS_ERRNO = 0x13,
|
||||
SEMIHOSTING_SYS_FLEN = 0x0C,
|
||||
SEMIHOSTING_SYS_GET_CMDLINE = 0x15,
|
||||
SEMIHOSTING_SYS_HEAPINFO = 0x16,
|
||||
SEMIHOSTING_SYS_ISERROR = 0x08,
|
||||
SEMIHOSTING_SYS_ISTTY = 0x09,
|
||||
SEMIHOSTING_SYS_OPEN = 0x01,
|
||||
SEMIHOSTING_SYS_READ = 0x06,
|
||||
SEMIHOSTING_SYS_READC = 0x07,
|
||||
SEMIHOSTING_SYS_REMOVE = 0x0E,
|
||||
SEMIHOSTING_SYS_RENAME = 0x0F,
|
||||
SEMIHOSTING_SYS_SEEK = 0x0A,
|
||||
SEMIHOSTING_SYS_SYSTEM = 0x12,
|
||||
SEMIHOSTING_SYS_TICKFREQ = 0x31,
|
||||
SEMIHOSTING_SYS_TIME = 0x11,
|
||||
SEMIHOSTING_SYS_TMPNAM = 0x0D,
|
||||
SEMIHOSTING_SYS_WRITE = 0x05,
|
||||
SEMIHOSTING_SYS_WRITEC = 0x03,
|
||||
SEMIHOSTING_SYS_WRITE0 = 0x04,
|
||||
|
||||
// Codes returned by SEMIHOSTING_ReportException
|
||||
ADP_Stopped_ApplicationExit = ((2 << 16) + 38),
|
||||
ADP_Stopped_RunTimeError = ((2 << 16) + 35),
|
||||
|
||||
};
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// SWI numbers and reason codes for RDI (Angel) monitors.
|
||||
#define AngelSWI_ARM 0x123456
|
||||
#ifdef __thumb__
|
||||
#define AngelSWI 0xAB
|
||||
#else
|
||||
#define AngelSWI AngelSWI_ARM
|
||||
#endif
|
||||
// For thumb only architectures use the BKPT instruction instead of SWI.
|
||||
#if defined(__ARM_ARCH_7M__) \
|
||||
|| defined(__ARM_ARCH_7EM__) \
|
||||
|| defined(__ARM_ARCH_6M__)
|
||||
#define AngelSWIInsn "bkpt"
|
||||
#define AngelSWIAsm bkpt
|
||||
#else
|
||||
#define AngelSWIInsn "swi"
|
||||
#define AngelSWIAsm swi
|
||||
#endif
|
||||
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
// Testing the local semihosting handler cannot use another BKPT, since this
|
||||
// configuration cannot trigger HaedFault exceptions while the debugger is
|
||||
// connected, so we use an illegal op code, that will trigger an
|
||||
// UsageFault exception.
|
||||
#define AngelSWITestFault "setend be"
|
||||
#define AngelSWITestFaultOpCode (0xB658)
|
||||
#endif
|
||||
|
||||
static inline int
|
||||
__attribute__ ((always_inline))
|
||||
call_host (int reason, void* arg)
|
||||
{
|
||||
int value;
|
||||
asm volatile (
|
||||
|
||||
" mov r0, %[rsn] \n"
|
||||
" mov r1, %[arg] \n"
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
" " AngelSWITestFault " \n"
|
||||
#else
|
||||
" " AngelSWIInsn " %[swi] \n"
|
||||
#endif
|
||||
" mov %[val], r0"
|
||||
|
||||
: [val] "=r" (value) /* Outputs */
|
||||
: [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */
|
||||
: "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"
|
||||
// Clobbers r0 and r1, and lr if in supervisor mode
|
||||
);
|
||||
|
||||
// Accordingly to page 13-77 of ARM DUI 0040D other registers
|
||||
// can also be clobbered. Some memory positions may also be
|
||||
// changed by a system call, so they should not be kept in
|
||||
// registers. Note: we are assuming the manual is right and
|
||||
// Angel is respecting the APCS.
|
||||
return value;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// Function used in _exit() to return the status code as Angel exception.
|
||||
static inline void
|
||||
__attribute__ ((always_inline,noreturn))
|
||||
report_exception (int reason)
|
||||
{
|
||||
call_host (SEMIHOSTING_ReportException, (void*) reason);
|
||||
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#endif // ARM_SEMIHOSTING_H_
|
||||
7
bootloader/system/include/cmsis/README_DEVICE_30x.txt
Normal file
7
bootloader/system/include/cmsis/README_DEVICE_30x.txt
Normal file
@ -0,0 +1,7 @@
|
||||
The stm32f30x.h and system_stm32f30x.h files are from stsw-stm32108.zip,
|
||||
the folder:
|
||||
|
||||
STM32F30x_DSP_StdPeriph_Lib_V1.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Include
|
||||
|
||||
The cmsis_device.h is added for convenience.
|
||||
|
||||
136
bootloader/system/include/cmsis/arm_common_tables.h
Normal file
136
bootloader/system/include/cmsis/arm_common_tables.h
Normal file
@ -0,0 +1,136 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. October 2015
|
||||
* $Revision: V.1.4.5 a
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
*
|
||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
/* extern const q31_t realCoefAQ31[1024]; */
|
||||
/* extern const q31_t realCoefBQ31[1024]; */
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
79
bootloader/system/include/cmsis/arm_const_structs.h
Normal file
79
bootloader/system/include/cmsis/arm_const_structs.h
Normal file
@ -0,0 +1,79 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. March 2015
|
||||
* $Revision: V.1.4.5
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
*
|
||||
* Description: This file has constant structs that are initialized for
|
||||
* user convenience. For example, some can be given as
|
||||
* arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
7154
bootloader/system/include/cmsis/arm_math.h
Normal file
7154
bootloader/system/include/cmsis/arm_math.h
Normal file
File diff suppressed because it is too large
Load Diff
734
bootloader/system/include/cmsis/cmsis_armcc.h
Normal file
734
bootloader/system/include/cmsis/cmsis_armcc.h
Normal file
@ -0,0 +1,734 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
|
||||
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in integer value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in two unsigned short values.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Reverse byte order in signed short value
|
||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x04) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
1800
bootloader/system/include/cmsis/cmsis_armcc_V6.h
Normal file
1800
bootloader/system/include/cmsis/cmsis_armcc_V6.h
Normal file
File diff suppressed because it is too large
Load Diff
17
bootloader/system/include/cmsis/cmsis_device.h
Normal file
17
bootloader/system/include/cmsis/cmsis_device.h
Normal file
@ -0,0 +1,17 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
#ifndef STM32F3_CMSIS_DEVICE_H_
|
||||
#define STM32F3_CMSIS_DEVICE_H_
|
||||
|
||||
#if defined(STM32F30X)
|
||||
#include "stm32f30x.h"
|
||||
#elif defined(STM32F37X)
|
||||
#include "stm32f37x.h"
|
||||
#else
|
||||
#error "No CMSIS header file"
|
||||
#endif
|
||||
|
||||
#endif // STM32F3_CMSIS_DEVICE_H_
|
||||
1373
bootloader/system/include/cmsis/cmsis_gcc.h
Normal file
1373
bootloader/system/include/cmsis/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
811
bootloader/system/include/cmsis/core_cm0.h
Normal file
811
bootloader/system/include/cmsis/core_cm0.h
Normal file
@ -0,0 +1,811 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wsign-conversion"
|
||||
#pragma GCC diagnostic ignored "-Wconversion"
|
||||
#pragma GCC diagnostic ignored "-Wunused-parameter"
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0 Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
927
bootloader/system/include/cmsis/core_cm0plus.h
Normal file
927
bootloader/system/include/cmsis/core_cm0plus.h
Normal file
@ -0,0 +1,927 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0plus.h
|
||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC
|
||||
#define __CORE_CM0PLUS_H_GENERIC
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wsign-conversion"
|
||||
#pragma GCC diagnostic ignored "-Wconversion"
|
||||
#pragma GCC diagnostic ignored "-Wunused-parameter"
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex-M0+
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS CM0+ definitions */
|
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_DEPENDANT
|
||||
#define __CORE_CM0PLUS_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0PLUS_REV
|
||||
#define __CM0PLUS_REV 0x0000U
|
||||
#warning "__CM0PLUS_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex-M0+ */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
- Core MPU Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
|
||||
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||
#else
|
||||
uint32_t RESERVED0;
|
||||
#endif
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
#endif
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||
|
||||
/*@} end of group CMSIS_MPU */
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0+ header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0+ Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
1776
bootloader/system/include/cmsis/core_cm3.h
Normal file
1776
bootloader/system/include/cmsis/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
1950
bootloader/system/include/cmsis/core_cm4.h
Normal file
1950
bootloader/system/include/cmsis/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
2525
bootloader/system/include/cmsis/core_cm7.h
Normal file
2525
bootloader/system/include/cmsis/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
87
bootloader/system/include/cmsis/core_cmFunc.h
Normal file
87
bootloader/system/include/cmsis/core_cmFunc.h
Normal file
@ -0,0 +1,87 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
87
bootloader/system/include/cmsis/core_cmInstr.h
Normal file
87
bootloader/system/include/cmsis/core_cmInstr.h
Normal file
@ -0,0 +1,87 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
96
bootloader/system/include/cmsis/core_cmSimd.h
Normal file
96
bootloader/system/include/cmsis/core_cmSimd.h
Normal file
@ -0,0 +1,96 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
926
bootloader/system/include/cmsis/core_sc000.h
Normal file
926
bootloader/system/include/cmsis/core_sc000.h
Normal file
@ -0,0 +1,926 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_sc000.h
|
||||
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_SC000_H_GENERIC
|
||||
#define __CORE_SC000_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup SC000
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS SC000 definitions */
|
||||
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_SC (000U) /*!< Cortex secure core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_SC000_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_SC000_H_DEPENDANT
|
||||
#define __CORE_SC000_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __SC000_REV
|
||||
#define __SC000_REV 0x0000U
|
||||
#warning "__SC000_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group SC000 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
- Core MPU Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED0[1U];
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
uint32_t RESERVED1[154U];
|
||||
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||
|
||||
/*@} end of group CMSIS_MPU */
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the SC000 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of SC000 Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_SC000_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
1745
bootloader/system/include/cmsis/core_sc300.h
Normal file
1745
bootloader/system/include/cmsis/core_sc300.h
Normal file
File diff suppressed because it is too large
Load Diff
6228
bootloader/system/include/cmsis/stm32f30x.h
Normal file
6228
bootloader/system/include/cmsis/stm32f30x.h
Normal file
File diff suppressed because it is too large
Load Diff
105
bootloader/system/include/cmsis/system_stm32f30x.h
Normal file
105
bootloader/system/include/cmsis/system_stm32f30x.h
Normal file
@ -0,0 +1,105 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f30x.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 04-September-2012
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f30x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F30X_H
|
||||
#define __SYSTEM_STM32F30X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F30x_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F30x_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F30X_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
94
bootloader/system/include/cortexm/ExceptionHandlers.h
Normal file
94
bootloader/system/include/cortexm/ExceptionHandlers.h
Normal file
@ -0,0 +1,94 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
#ifndef CORTEXM_EXCEPTION_HANDLERS_H_
|
||||
#define CORTEXM_EXCEPTION_HANDLERS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#if defined(DEBUG)
|
||||
#define __DEBUG_BKPT() asm volatile ("bkpt 0")
|
||||
#endif
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
// External references to cortexm_handlers.c
|
||||
|
||||
extern void
|
||||
Reset_Handler (void);
|
||||
extern void
|
||||
NMI_Handler (void);
|
||||
extern void
|
||||
HardFault_Handler (void);
|
||||
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
extern void
|
||||
MemManage_Handler (void);
|
||||
extern void
|
||||
BusFault_Handler (void);
|
||||
extern void
|
||||
UsageFault_Handler (void);
|
||||
extern void
|
||||
DebugMon_Handler (void);
|
||||
#endif
|
||||
|
||||
extern void
|
||||
SVC_Handler (void);
|
||||
|
||||
extern void
|
||||
PendSV_Handler (void);
|
||||
extern void
|
||||
SysTick_Handler (void);
|
||||
|
||||
// Exception Stack Frame of the Cortex-M3 or Cortex-M4 processor.
|
||||
typedef struct
|
||||
{
|
||||
uint32_t r0;
|
||||
uint32_t r1;
|
||||
uint32_t r2;
|
||||
uint32_t r3;
|
||||
uint32_t r12;
|
||||
uint32_t lr;
|
||||
uint32_t pc;
|
||||
uint32_t psr;
|
||||
#if defined(__ARM_ARCH_7EM__)
|
||||
uint32_t s[16];
|
||||
#endif
|
||||
} ExceptionStackFrame;
|
||||
|
||||
#if defined(TRACE)
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
void
|
||||
dumpExceptionStack (ExceptionStackFrame* frame, uint32_t cfsr, uint32_t mmfar,
|
||||
uint32_t bfar, uint32_t lr);
|
||||
#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
#if defined(__ARM_ARCH_6M__)
|
||||
void
|
||||
dumpExceptionStack (ExceptionStackFrame* frame, uint32_t lr);
|
||||
#endif // defined(__ARM_ARCH_6M__)
|
||||
#endif // defined(TRACE)
|
||||
|
||||
void
|
||||
HardFault_Handler_C (ExceptionStackFrame* frame, uint32_t lr);
|
||||
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
void
|
||||
UsageFault_Handler_C (ExceptionStackFrame* frame, uint32_t lr);
|
||||
void
|
||||
BusFault_Handler_C (ExceptionStackFrame* frame, uint32_t lr);
|
||||
#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#endif // CORTEXM_EXCEPTION_HANDLERS_H_
|
||||
146
bootloader/system/include/diag/Trace.h
Normal file
146
bootloader/system/include/diag/Trace.h
Normal file
@ -0,0 +1,146 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
#ifndef DIAG_TRACE_H_
|
||||
#define DIAG_TRACE_H_
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include <unistd.h>
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// The trace device is an independent output channel, intended for debug
|
||||
// purposes.
|
||||
//
|
||||
// The API is simple, and mimics the standard output calls:
|
||||
// - trace_printf()
|
||||
// - trace_puts()
|
||||
// - trace_putchar();
|
||||
//
|
||||
// The implementation is done in
|
||||
// - trace_write()
|
||||
//
|
||||
// Trace support is enabled by adding the TRACE definition.
|
||||
// By default the trace messages are forwarded to the ITM output,
|
||||
// but can be rerouted via any device or completely suppressed by
|
||||
// changing the definitions required in system/src/diag/trace_impl.c
|
||||
// (currently OS_USE_TRACE_ITM, OS_USE_TRACE_SEMIHOSTING_DEBUG/_STDOUT).
|
||||
//
|
||||
// When TRACE is not defined, all functions are inlined to empty bodies.
|
||||
// This has the advantage that the trace call do not need to be conditionally
|
||||
// compiled with #ifdef TRACE/#endif
|
||||
|
||||
|
||||
#if defined(TRACE)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
void
|
||||
trace_initialize(void);
|
||||
|
||||
// Implementation dependent
|
||||
ssize_t
|
||||
trace_write(const char* buf, size_t nbyte);
|
||||
|
||||
// ----- Portable -----
|
||||
|
||||
int
|
||||
trace_printf(const char* format, ...);
|
||||
|
||||
int
|
||||
trace_puts(const char *s);
|
||||
|
||||
int
|
||||
trace_putchar(int c);
|
||||
|
||||
void
|
||||
trace_dump_args(int argc, char* argv[]);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#else // !defined(TRACE)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
inline void
|
||||
trace_initialize(void);
|
||||
|
||||
// Implementation dependent
|
||||
inline ssize_t
|
||||
trace_write(const char* buf, size_t nbyte);
|
||||
|
||||
inline int
|
||||
trace_printf(const char* format, ...);
|
||||
|
||||
inline int
|
||||
trace_puts(const char *s);
|
||||
|
||||
inline int
|
||||
trace_putchar(int c);
|
||||
|
||||
inline void
|
||||
trace_dump_args(int argc, char* argv[]);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
inline void
|
||||
__attribute__((always_inline))
|
||||
trace_initialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
// Empty definitions when trace is not defined
|
||||
inline ssize_t
|
||||
__attribute__((always_inline))
|
||||
trace_write(const char* buf __attribute__((unused)),
|
||||
size_t nbyte __attribute__((unused)))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
inline int
|
||||
__attribute__((always_inline))
|
||||
trace_printf(const char* format __attribute__((unused)), ...)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
inline int
|
||||
__attribute__((always_inline))
|
||||
trace_puts(const char *s __attribute__((unused)))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
inline int
|
||||
__attribute__((always_inline))
|
||||
trace_putchar(int c)
|
||||
{
|
||||
return c;
|
||||
}
|
||||
|
||||
inline void
|
||||
__attribute__((always_inline))
|
||||
trace_dump_args(int argc __attribute__((unused)),
|
||||
char* argv[] __attribute__((unused)))
|
||||
{
|
||||
}
|
||||
|
||||
#endif // defined(TRACE)
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#endif // DIAG_TRACE_H_
|
||||
@ -0,0 +1,4 @@
|
||||
These files are from stsw-stm32108.zip, the folder:
|
||||
|
||||
STM32F30x_DSP_StdPeriph_Lib_V1.0.0/Libraries/STM32F30x_StdPeriph_Driver/inc
|
||||
|
||||
831
bootloader/system/include/stm32f3-stdperiph/stm32f30x_adc.h
Normal file
831
bootloader/system/include/stm32f3-stdperiph/stm32f30x_adc.h
Normal file
@ -0,0 +1,831 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_ADC_H
|
||||
#define __STM32F30x_ADC_H
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpadded"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t ADC_Resolution; /*!< Configures the ADC resolution.
|
||||
This parameter can be a value of @ref ADC_resolution */
|
||||
uint32_t ADC_ExternalTrigConvEvent; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
uint32_t ADC_ExternalTrigEventEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_external_trigger_edge_for_regular_channels_conversion */
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
uint32_t ADC_OverrunMode; /*!< Specifies the way data overrun are managed.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t ADC_AutoInjMode; /*!< Enable/disable automatic injected group conversion after
|
||||
regular group conversion.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint8_t ADC_NbrOfRegChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t ADC_ExternalTrigInjecConvEvent; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of injected channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_Injected_channels_conversion */
|
||||
uint32_t ADC_ExternalTrigInjecEventEdge; /*!< Select the external trigger edge and enable the trigger of an injected group.
|
||||
This parameter can be a value of
|
||||
@ref ADC_external_trigger_edge_for_Injected_channels_conversion */
|
||||
uint8_t ADC_NbrOfInjecChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for injected channel group.
|
||||
This parameter must range from 1 to 4. */
|
||||
uint32_t ADC_InjecSequence1;
|
||||
uint32_t ADC_InjecSequence2;
|
||||
uint32_t ADC_InjecSequence3;
|
||||
uint32_t ADC_InjecSequence4;
|
||||
}ADC_InjectedInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /*!< Configures the ADC to operate in
|
||||
independent or multi mode.
|
||||
This parameter can be a value of @ref ADC_mode */
|
||||
uint32_t ADC_Clock; /*!< Select the clock of the ADC. The clock is common for both master
|
||||
and slave ADCs.
|
||||
This parameter can be a value of @ref ADC_Clock */
|
||||
uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
|
||||
This parameter can be a value of
|
||||
@ref ADC_Direct_memory_access_mode_for_multi_mode */
|
||||
uint32_t ADC_DMAMode; /*!< Configures the DMA mode for ADC.
|
||||
This parameter can be a value of @ref ADC_DMA_Mode_definition */
|
||||
uint8_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
This parameter can be a value between 0x0 and 0xF */
|
||||
|
||||
}ADC_CommonInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3) || \
|
||||
((PERIPH) == ADC4))
|
||||
|
||||
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||
((PERIPH) == ADC2) || \
|
||||
((PERIPH) == ADC3) || \
|
||||
((PERIPH) == ADC4))
|
||||
|
||||
/** @defgroup ADC_ContinuousConvMode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ContinuousConvMode_Enable ((uint32_t)0x00002000) /*!< ADC continuous conversion mode enable */
|
||||
#define ADC_ContinuousConvMode_Disable ((uint32_t)0x00000000) /*!< ADC continuous conversion mode disable */
|
||||
#define IS_ADC_CONVMODE(MODE) (((MODE) == ADC_ContinuousConvMode_Enable) || \
|
||||
((MODE) == ADC_ContinuousConvMode_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_OverunMode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OverrunMode_Enable ((uint32_t)0x00001000) /*!< ADC Overrun Mode enable */
|
||||
#define ADC_OverrunMode_Disable ((uint32_t)0x00000000) /*!< ADC Overrun Mode disable */
|
||||
#define IS_ADC_OVRUNMODE(MODE) (((MODE) == ADC_OverrunMode_Enable) || \
|
||||
((MODE) == ADC_OverrunMode_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_AutoInjecMode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AutoInjec_Enable ((uint32_t)0x02000000) /*!< ADC Auto injected Mode enable */
|
||||
#define ADC_AutoInjec_Disable ((uint32_t)0x00000000) /*!< ADC Auto injected Mode disable */
|
||||
#define IS_ADC_AUTOINJECMODE(MODE) (((MODE) == ADC_AutoInjec_Enable) || \
|
||||
((MODE) == ADC_AutoInjec_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Resolution_12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
|
||||
#define ADC_Resolution_10b ((uint32_t)0x00000008) /*!< ADC 10-bit resolution */
|
||||
#define ADC_Resolution_8b ((uint32_t)0x00000010) /*!< ADC 8-bit resolution */
|
||||
#define ADC_Resolution_6b ((uint32_t)0x00000018) /*!< ADC 6-bit resolution */
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
|
||||
((RESOLUTION) == ADC_Resolution_10b) || \
|
||||
((RESOLUTION) == ADC_Resolution_8b) || \
|
||||
((RESOLUTION) == ADC_Resolution_6b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
|
||||
#define ADC_ExternalTrigEventEdge_RisingEdge ((uint16_t)0x0400) /*!< ADC external trigger rising edge for regular conversion */
|
||||
#define ADC_ExternalTrigEventEdge_FallingEdge ((uint16_t)0x0800) /*!< ADC ADC external trigger falling edge for regular conversion */
|
||||
#define ADC_ExternalTrigEventEdge_BothEdge ((uint16_t)0x0C00) /*!< ADC ADC external trigger both edges for regular conversion */
|
||||
|
||||
#define IS_EXTERNALTRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigEventEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigEventEdge_RisingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigEventEdge_FallingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigEventEdge_BothEdge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_Injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigInjecEventEdge_None ((uint16_t)0x0000) /*!< ADC No external trigger for regular conversion */
|
||||
#define ADC_ExternalTrigInjecEventEdge_RisingEdge ((uint16_t)0x0040) /*!< ADC external trigger rising edge for injected conversion */
|
||||
#define ADC_ExternalTrigInjecEventEdge_FallingEdge ((uint16_t)0x0080) /*!< ADC external trigger falling edge for injected conversion */
|
||||
#define ADC_ExternalTrigInjecEventEdge_BothEdge ((uint16_t)0x00C0) /*!< ADC external trigger both edges for injected conversion */
|
||||
|
||||
#define IS_EXTERNALTRIGINJ_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecEventEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecEventEdge_RisingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecEventEdge_FallingEdge) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecEventEdge_BothEdge))
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger event 0 */
|
||||
#define ADC_ExternalTrigConvEvent_1 ((uint16_t)0x0040) /*!< ADC external trigger event 1 */
|
||||
#define ADC_ExternalTrigConvEvent_2 ((uint16_t)0x0080) /*!< ADC external trigger event 2 */
|
||||
#define ADC_ExternalTrigConvEvent_3 ((uint16_t)0x00C0) /*!< ADC external trigger event 3 */
|
||||
#define ADC_ExternalTrigConvEvent_4 ((uint16_t)0x0100) /*!< ADC external trigger event 4 */
|
||||
#define ADC_ExternalTrigConvEvent_5 ((uint16_t)0x0140) /*!< ADC external trigger event 5 */
|
||||
#define ADC_ExternalTrigConvEvent_6 ((uint16_t)0x0180) /*!< ADC external trigger event 6 */
|
||||
#define ADC_ExternalTrigConvEvent_7 ((uint16_t)0x01C0) /*!< ADC external trigger event 7 */
|
||||
#define ADC_ExternalTrigConvEvent_8 ((uint16_t)0x0200) /*!< ADC external trigger event 8 */
|
||||
#define ADC_ExternalTrigConvEvent_9 ((uint16_t)0x0240) /*!< ADC external trigger event 9 */
|
||||
#define ADC_ExternalTrigConvEvent_10 ((uint16_t)0x0280) /*!< ADC external trigger event 10 */
|
||||
#define ADC_ExternalTrigConvEvent_11 ((uint16_t)0x02C0) /*!< ADC external trigger event 11 */
|
||||
#define ADC_ExternalTrigConvEvent_12 ((uint16_t)0x0300) /*!< ADC external trigger event 12 */
|
||||
#define ADC_ExternalTrigConvEvent_13 ((uint16_t)0x0340) /*!< ADC external trigger event 13 */
|
||||
#define ADC_ExternalTrigConvEvent_14 ((uint16_t)0x0380) /*!< ADC external trigger event 14 */
|
||||
#define ADC_ExternalTrigConvEvent_15 ((uint16_t)0x03C0) /*!< ADC external trigger event 15 */
|
||||
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConvEvent_0) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_5) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_6) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_7) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_8) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_9) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_10) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_11) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_12) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_13) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_14) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConvEvent_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_Injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ExternalTrigInjecConvEvent_0 ((uint16_t)0x0000) /*!< ADC external trigger for injected conversion event 0 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_1 ((uint16_t)0x0004) /*!< ADC external trigger for injected conversion event 1 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_2 ((uint16_t)0x0008) /*!< ADC external trigger for injected conversion event 2 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_3 ((uint16_t)0x000C) /*!< ADC external trigger for injected conversion event 3 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_4 ((uint16_t)0x0010) /*!< ADC external trigger for injected conversion event 4 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_5 ((uint16_t)0x0014) /*!< ADC external trigger for injected conversion event 5 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_6 ((uint16_t)0x0018) /*!< ADC external trigger for injected conversion event 6 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_7 ((uint16_t)0x001C) /*!< ADC external trigger for injected conversion event 7 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_8 ((uint16_t)0x0020) /*!< ADC external trigger for injected conversion event 8 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_9 ((uint16_t)0x0024) /*!< ADC external trigger for injected conversion event 9 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_10 ((uint16_t)0x0028) /*!< ADC external trigger for injected conversion event 10 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_11 ((uint16_t)0x002C) /*!< ADC external trigger for injected conversion event 11 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_12 ((uint16_t)0x0030) /*!< ADC external trigger for injected conversion event 12 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_13 ((uint16_t)0x0034) /*!< ADC external trigger for injected conversion event 13 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_14 ((uint16_t)0x0038) /*!< ADC external trigger for injected conversion event 14 */
|
||||
#define ADC_ExternalTrigInjecConvEvent_15 ((uint16_t)0x003C) /*!< ADC external trigger for injected conversion event 15 */
|
||||
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConvEvent_0) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_5) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_6) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_7) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_8) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_9) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_10) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_11) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_12) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_13) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_14) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConvEvent_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000) /*!< ADC Data alignment right */
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000020) /*!< ADC Data alignment left */
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Channel_1 ((uint8_t)0x01) /*!< ADC Channel 1 */
|
||||
#define ADC_Channel_2 ((uint8_t)0x02) /*!< ADC Channel 2 */
|
||||
#define ADC_Channel_3 ((uint8_t)0x03) /*!< ADC Channel 3 */
|
||||
#define ADC_Channel_4 ((uint8_t)0x04) /*!< ADC Channel 4 */
|
||||
#define ADC_Channel_5 ((uint8_t)0x05) /*!< ADC Channel 5 */
|
||||
#define ADC_Channel_6 ((uint8_t)0x06) /*!< ADC Channel 6 */
|
||||
#define ADC_Channel_7 ((uint8_t)0x07) /*!< ADC Channel 7 */
|
||||
#define ADC_Channel_8 ((uint8_t)0x08) /*!< ADC Channel 8 */
|
||||
#define ADC_Channel_9 ((uint8_t)0x09) /*!< ADC Channel 9 */
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A) /*!< ADC Channel 10 */
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B) /*!< ADC Channel 11 */
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C) /*!< ADC Channel 12 */
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D) /*!< ADC Channel 13 */
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E) /*!< ADC Channel 14 */
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F) /*!< ADC Channel 15 */
|
||||
#define ADC_Channel_16 ((uint8_t)0x10) /*!< ADC Channel 16 */
|
||||
#define ADC_Channel_17 ((uint8_t)0x11) /*!< ADC Channel 17 */
|
||||
#define ADC_Channel_18 ((uint8_t)0x12) /*!< ADC Channel 18 */
|
||||
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_18)
|
||||
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_17)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || \
|
||||
((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || \
|
||||
((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || \
|
||||
((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || \
|
||||
((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || \
|
||||
((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || \
|
||||
((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || \
|
||||
((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || \
|
||||
((CHANNEL) == ADC_Channel_17) || \
|
||||
((CHANNEL) == ADC_Channel_18))
|
||||
#define IS_ADC_DIFFCHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || \
|
||||
((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || \
|
||||
((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || \
|
||||
((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || \
|
||||
((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || \
|
||||
((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || \
|
||||
((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000) /*!< ADC independent mode */
|
||||
#define ADC_Mode_CombRegSimulInjSimul ((uint32_t)0x00000001) /*!< ADC multi ADC mode: Combined Regular simultaneous injected simultaneous mode */
|
||||
#define ADC_Mode_CombRegSimulAltTrig ((uint32_t)0x00000002) /*!< ADC multi ADC mode: Combined Regular simultaneous Alternate trigger mode */
|
||||
#define ADC_Mode_InjSimul ((uint32_t)0x00000005) /*!< ADC multi ADC mode: Injected simultaneous mode */
|
||||
#define ADC_Mode_RegSimul ((uint32_t)0x00000006) /*!< ADC multi ADC mode: Regular simultaneous mode */
|
||||
#define ADC_Mode_Interleave ((uint32_t)0x00000007) /*!< ADC multi ADC mode: Interleave mode */
|
||||
#define ADC_Mode_AltTrig ((uint32_t)0x00000009) /*!< ADC multi ADC mode: Alternate Trigger mode */
|
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
||||
((MODE) == ADC_Mode_CombRegSimulInjSimul) || \
|
||||
((MODE) == ADC_Mode_CombRegSimulAltTrig) || \
|
||||
((MODE) == ADC_Mode_InjSimul) || \
|
||||
((MODE) == ADC_Mode_RegSimul) || \
|
||||
((MODE) == ADC_Mode_Interleave) || \
|
||||
((MODE) == ADC_Mode_AltTrig))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Clock
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Clock_AsynClkMode ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
|
||||
#define ADC_Clock_SynClkModeDiv1 ((uint32_t)0x00010000) /*!< Synchronous clock mode divided by 1 */
|
||||
#define ADC_Clock_SynClkModeDiv2 ((uint32_t)0x00020000) /*!< Synchronous clock mode divided by 2 */
|
||||
#define ADC_Clock_SynClkModeDiv4 ((uint32_t)0x00030000) /*!< Synchronous clock mode divided by 4 */
|
||||
#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_Clock_AsynClkMode) ||\
|
||||
((CLOCK) == ADC_Clock_SynClkModeDiv1) ||\
|
||||
((CLOCK) == ADC_Clock_SynClkModeDiv2)||\
|
||||
((CLOCK) == ADC_Clock_SynClkModeDiv4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /*!< DMA mode disabled */
|
||||
#define ADC_DMAAccessMode_1 ((uint32_t)0x00008000) /*!< DMA mode enabled for 12 and 10-bit resolution (6 bit) */
|
||||
#define ADC_DMAAccessMode_2 ((uint32_t)0x0000C000) /*!< DMA mode enabled for 8 and 6-bit resolution (8bit) */
|
||||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
|
||||
((MODE) == ADC_DMAAccessMode_1) || \
|
||||
((MODE) == ADC_DMAAccessMode_2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_sampling_time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) /*!< ADC sampling time 1.5 cycle */
|
||||
#define ADC_SampleTime_2Cycles5 ((uint8_t)0x01) /*!< ADC sampling time 2.5 cycles */
|
||||
#define ADC_SampleTime_4Cycles5 ((uint8_t)0x02) /*!< ADC sampling time 4.5 cycles */
|
||||
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x03) /*!< ADC sampling time 7.5 cycles */
|
||||
#define ADC_SampleTime_19Cycles5 ((uint8_t)0x04) /*!< ADC sampling time 19.5 cycles */
|
||||
#define ADC_SampleTime_61Cycles5 ((uint8_t)0x05) /*!< ADC sampling time 61.5 cycles */
|
||||
#define ADC_SampleTime_181Cycles5 ((uint8_t)0x06) /*!< ADC sampling time 181.5 cycles */
|
||||
#define ADC_SampleTime_601Cycles5 ((uint8_t)0x07) /*!< ADC sampling time 601.5 cycles */
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_2Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_4Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_7Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_19Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_61Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_181Cycles5) || \
|
||||
((TIME) == ADC_SampleTime_601Cycles5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_InjectedChannel_1 ADC_Channel_1 /*!< ADC Injected channel 1 */
|
||||
#define ADC_InjectedChannel_2 ADC_Channel_2 /*!< ADC Injected channel 2 */
|
||||
#define ADC_InjectedChannel_3 ADC_Channel_3 /*!< ADC Injected channel 3 */
|
||||
#define ADC_InjectedChannel_4 ADC_Channel_4 /*!< ADC Injected channel 4 */
|
||||
#define ADC_InjectedChannel_5 ADC_Channel_5 /*!< ADC Injected channel 5 */
|
||||
#define ADC_InjectedChannel_6 ADC_Channel_6 /*!< ADC Injected channel 6 */
|
||||
#define ADC_InjectedChannel_7 ADC_Channel_7 /*!< ADC Injected channel 7 */
|
||||
#define ADC_InjectedChannel_8 ADC_Channel_8 /*!< ADC Injected channel 8 */
|
||||
#define ADC_InjectedChannel_9 ADC_Channel_9 /*!< ADC Injected channel 9 */
|
||||
#define ADC_InjectedChannel_10 ADC_Channel_10 /*!< ADC Injected channel 10 */
|
||||
#define ADC_InjectedChannel_11 ADC_Channel_11 /*!< ADC Injected channel 11 */
|
||||
#define ADC_InjectedChannel_12 ADC_Channel_12 /*!< ADC Injected channel 12 */
|
||||
#define ADC_InjectedChannel_13 ADC_Channel_13 /*!< ADC Injected channel 13 */
|
||||
#define ADC_InjectedChannel_14 ADC_Channel_14 /*!< ADC Injected channel 14 */
|
||||
#define ADC_InjectedChannel_15 ADC_Channel_15 /*!< ADC Injected channel 15 */
|
||||
#define ADC_InjectedChannel_16 ADC_Channel_16 /*!< ADC Injected channel 16 */
|
||||
#define ADC_InjectedChannel_17 ADC_Channel_17 /*!< ADC Injected channel 17 */
|
||||
#define ADC_InjectedChannel_18 ADC_Channel_18 /*!< ADC Injected channel 18 */
|
||||
|
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_5) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_6) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_7) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_8) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_9) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_10) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_11) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_12) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_13) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_14) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_15) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_16) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_17) ||\
|
||||
((CHANNEL) == ADC_InjectedChannel_18))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_Sequence_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_InjectedSequence_1 ADC_Channel_1 /*!< ADC Injected sequence 1 */
|
||||
#define ADC_InjectedSequence_2 ADC_Channel_2 /*!< ADC Injected sequence 2 */
|
||||
#define ADC_InjectedSequence_3 ADC_Channel_3 /*!< ADC Injected sequence 3 */
|
||||
#define ADC_InjectedSequence_4 ADC_Channel_4 /*!< ADC Injected sequence 4 */
|
||||
#define IS_ADC_INJECTED_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_InjectedSequence_1) || \
|
||||
((SEQUENCE) == ADC_InjectedSequence_2) || \
|
||||
((SEQUENCE) == ADC_InjectedSequence_3) || \
|
||||
((SEQUENCE) == ADC_InjectedSequence_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00C00000) /*!< ADC Analog watchdog single regular mode */
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x01400000) /*!< ADC Analog watchdog single injected mode */
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x01C00000) /*!< ADC Analog watchdog single regular or injected mode */
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) /*!< ADC Analog watchdog all regular mode */
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x01000000) /*!< ADC Analog watchdog all injected mode */
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x01800000) /*!< ADC Analog watchdog all regular and all injected mode */
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) /*!< ADC Analog watchdog off */
|
||||
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Calibration_Mode_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CalibrationMode_Single ((uint32_t)0x00000000) /*!< ADC Calibration for single ended channel */
|
||||
#define ADC_CalibrationMode_Differential ((uint32_t)0x40000000) /*!< ADC Calibration for differential channel */
|
||||
|
||||
#define IS_ADC_CALIBRATION_MODE(MODE) (((MODE) == ADC_CalibrationMode_Single) ||((MODE) == ADC_CalibrationMode_Differential))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_DMA_Mode_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAMode_OneShot ((uint32_t)0x00000000) /*!< ADC DMA Oneshot mode */
|
||||
#define ADC_DMAMode_Circular ((uint32_t)0x00000002) /*!< ADC DMA circular mode */
|
||||
|
||||
#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || ((MODE) == ADC_DMAMode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_IT_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) interrupt source */
|
||||
#define ADC_IT_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling interrupt source */
|
||||
#define ADC_IT_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion interrupt source */
|
||||
#define ADC_IT_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions interrupt source */
|
||||
#define ADC_IT_OVR ((uint16_t)0x0010) /*!< ADC overrun interrupt source */
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion interrupt source */
|
||||
#define ADC_IT_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions interrupt source */
|
||||
#define ADC_IT_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 interrupt source */
|
||||
#define ADC_IT_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 interrupt source */
|
||||
#define ADC_IT_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 interrupt source */
|
||||
#define ADC_IT_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow interrupt source */
|
||||
|
||||
|
||||
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF800) == 0x0000) && ((IT) != 0x0000))
|
||||
|
||||
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \
|
||||
((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \
|
||||
((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \
|
||||
((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \
|
||||
((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \
|
||||
((IT) == ADC_IT_JQOVF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_RDY ((uint16_t)0x0001) /*!< ADC Ready (ADRDY) flag */
|
||||
#define ADC_FLAG_EOSMP ((uint16_t)0x0002) /*!< ADC End of Sampling flag */
|
||||
#define ADC_FLAG_EOC ((uint16_t)0x0004) /*!< ADC End of Regular Conversion flag */
|
||||
#define ADC_FLAG_EOS ((uint16_t)0x0008) /*!< ADC End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_OVR ((uint16_t)0x0010) /*!< ADC overrun flag */
|
||||
#define ADC_FLAG_JEOC ((uint16_t)0x0020) /*!< ADC End of Injected Conversion flag */
|
||||
#define ADC_FLAG_JEOS ((uint16_t)0x0040) /*!< ADC End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_AWD1 ((uint16_t)0x0080) /*!< ADC Analog watchdog 1 flag */
|
||||
#define ADC_FLAG_AWD2 ((uint16_t)0x0100) /*!< ADC Analog watchdog 2 flag */
|
||||
#define ADC_FLAG_AWD3 ((uint16_t)0x0200) /*!< ADC Analog watchdog 3 flag */
|
||||
#define ADC_FLAG_JQOVF ((uint16_t)0x0400) /*!< ADC Injected Context Queue Overflow flag */
|
||||
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF800) == 0x0000) && ((FLAG) != 0x0000))
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
|
||||
((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
|
||||
((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \
|
||||
((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \
|
||||
((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \
|
||||
((FLAG) == ADC_FLAG_JQOVF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Common_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_MSTRDY ((uint32_t)0x00000001) /*!< ADC Master Ready (ADRDY) flag */
|
||||
#define ADC_FLAG_MSTEOSMP ((uint32_t)0x00000002) /*!< ADC Master End of Sampling flag */
|
||||
#define ADC_FLAG_MSTEOC ((uint32_t)0x00000004) /*!< ADC Master End of Regular Conversion flag */
|
||||
#define ADC_FLAG_MSTEOS ((uint32_t)0x00000008) /*!< ADC Master End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_MSTOVR ((uint32_t)0x00000010) /*!< ADC Master overrun flag */
|
||||
#define ADC_FLAG_MSTJEOC ((uint32_t)0x00000020) /*!< ADC Master End of Injected Conversion flag */
|
||||
#define ADC_FLAG_MSTJEOS ((uint32_t)0x00000040) /*!< ADC Master End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_MSTAWD1 ((uint32_t)0x00000080) /*!< ADC Master Analog watchdog 1 flag */
|
||||
#define ADC_FLAG_MSTAWD2 ((uint32_t)0x00000100) /*!< ADC Master Analog watchdog 2 flag */
|
||||
#define ADC_FLAG_MSTAWD3 ((uint32_t)0x00000200) /*!< ADC Master Analog watchdog 3 flag */
|
||||
#define ADC_FLAG_MSTJQOVF ((uint32_t)0x00000400) /*!< ADC Master Injected Context Queue Overflow flag */
|
||||
|
||||
#define ADC_FLAG_SLVRDY ((uint32_t)0x00010000) /*!< ADC Slave Ready (ADRDY) flag */
|
||||
#define ADC_FLAG_SLVEOSMP ((uint32_t)0x00020000) /*!< ADC Slave End of Sampling flag */
|
||||
#define ADC_FLAG_SLVEOC ((uint32_t)0x00040000) /*!< ADC Slave End of Regular Conversion flag */
|
||||
#define ADC_FLAG_SLVEOS ((uint32_t)0x00080000) /*!< ADC Slave End of Regular sequence of Conversions flag */
|
||||
#define ADC_FLAG_SLVOVR ((uint32_t)0x00100000) /*!< ADC Slave overrun flag */
|
||||
#define ADC_FLAG_SLVJEOC ((uint32_t)0x00200000) /*!< ADC Slave End of Injected Conversion flag */
|
||||
#define ADC_FLAG_SLVJEOS ((uint32_t)0x00400000) /*!< ADC Slave End of Injected sequence of Conversions flag */
|
||||
#define ADC_FLAG_SLVAWD1 ((uint32_t)0x00800000) /*!< ADC Slave Analog watchdog 1 flag */
|
||||
#define ADC_FLAG_SLVAWD2 ((uint32_t)0x01000000) /*!< ADC Slave Analog watchdog 2 flag */
|
||||
#define ADC_FLAG_SLVAWD3 ((uint32_t)0x02000000) /*!< ADC Slave Analog watchdog 3 flag */
|
||||
#define ADC_FLAG_SLVJQOVF ((uint32_t)0x04000000) /*!< ADC Slave Injected Context Queue Overflow flag */
|
||||
|
||||
#define IS_ADC_CLEAR_COMMONFLAG(FLAG) ((((FLAG) & (uint32_t)0xF800F800) == 0x0000) && ((FLAG) != 0x00000000))
|
||||
#define IS_ADC_GET_COMMONFLAG(FLAG) (((FLAG) == ADC_FLAG_MSTRDY) || ((FLAG) == ADC_FLAG_MSTEOSMP) || \
|
||||
((FLAG) == ADC_FLAG_MSTEOC) || ((FLAG) == ADC_FLAG_MSTEOS) || \
|
||||
((FLAG) == ADC_FLAG_MSTOVR) || ((FLAG) == ADC_FLAG_MSTEOS) || \
|
||||
((FLAG) == ADC_FLAG_MSTJEOS) || ((FLAG) == ADC_FLAG_MSTAWD1) || \
|
||||
((FLAG) == ADC_FLAG_MSTAWD2) || ((FLAG) == ADC_FLAG_MSTAWD3) || \
|
||||
((FLAG) == ADC_FLAG_MSTJQOVF) || \
|
||||
((FLAG) == ADC_FLAG_SLVRDY) || ((FLAG) == ADC_FLAG_SLVEOSMP) || \
|
||||
((FLAG) == ADC_FLAG_SLVEOC) || ((FLAG) == ADC_FLAG_SLVEOS) || \
|
||||
((FLAG) == ADC_FLAG_SLVOVR) || ((FLAG) == ADC_FLAG_SLVEOS) || \
|
||||
((FLAG) == ADC_FLAG_SLVJEOS) || ((FLAG) == ADC_FLAG_SLVAWD1) || \
|
||||
((FLAG) == ADC_FLAG_SLVAWD2) || ((FLAG) == ADC_FLAG_SLVAWD3) || \
|
||||
((FLAG) == ADC_FLAG_SLVJQOVF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_two_sampling_delay_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_TWOSAMPLING_DELAY(DELAY) (((DELAY) <= 0xF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the ADC configuration to the default reset state *****/
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_InjectedInit(ADC_TypeDef* ADCx, ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
|
||||
void ADC_InjectedStructInit(ADC_InjectedInitTypeDef* ADC_InjectedInitStruct);
|
||||
void ADC_CommonInit(ADC_TypeDef* ADCx, ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetCalibrationValue(ADC_TypeDef* ADCx);
|
||||
void ADC_SetCalibrationValue(ADC_TypeDef* ADCx, uint32_t ADC_Calibration);
|
||||
void ADC_SelectCalibrationMode(ADC_TypeDef* ADCx, uint32_t ADC_CalibrationMode);
|
||||
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_DisableCmd(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetDisableCmdStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_VoltageRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_SelectDifferentialMode(ADC_TypeDef* ADCx, uint8_t ADC_Channel, FunctionalState NewState);
|
||||
void ADC_SelectQueueOfContextMode(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_AutoDelayCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Analog Watchdog configuration functions ************************************/
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
|
||||
void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef* ADCx, uint8_t HighThreshold, uint8_t LowThreshold);
|
||||
void ADC_AnalogWatchdog1SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_AnalogWatchdog2SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_AnalogWatchdog3SingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
|
||||
/* Temperature Sensor, Vrefint and Vbat management function */
|
||||
void ADC_TempSensorCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_VrefintCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_VbatCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Channels Configuration functions ***********************************/
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_RegularChannelSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t SequencerLength);
|
||||
void ADC_ExternalTriggerConfig(ADC_TypeDef* ADCx, uint16_t ADC_ExternalTrigConvEvent, uint16_t ADC_ExternalTrigEventEdge);
|
||||
|
||||
void ADC_StartConversion(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetStartConversionStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_StopConversion(ADC_TypeDef* ADCx);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
uint32_t ADC_GetDualModeConversionValue(ADC_TypeDef* ADCx);
|
||||
|
||||
void ADC_SetChannelOffset1(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
void ADC_SetChannelOffset2(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
void ADC_SetChannelOffset3(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
void ADC_SetChannelOffset4(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint16_t Offset);
|
||||
|
||||
void ADC_ChannelOffset1Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ChannelOffset2Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ChannelOffset3Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ChannelOffset4Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Regular Channels DMA Configuration functions *******************************/
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMAConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMAMode);
|
||||
|
||||
/* Injected channels Configuration functions **********************************/
|
||||
void ADC_InjectedChannelSampleTimeConfig(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint8_t ADC_SampleTime);
|
||||
void ADC_StartInjectedConversion(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetStartInjectedConversionStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_StopInjectedConversion(ADC_TypeDef* ADCx);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||
|
||||
/* ADC Dual Modes Configuration functions *************************************/
|
||||
FlagStatus ADC_GetCommonFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
void ADC_ClearCommonFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
654
bootloader/system/include/stm32f3-stdperiph/stm32f30x_can.h
Normal file
654
bootloader/system/include/stm32f3-stdperiph/stm32f30x_can.h
Normal file
@ -0,0 +1,654 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_can.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_CAN_H
|
||||
#define __STM32F30x_CAN_H
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpadded"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1))
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
|
||||
It ranges from 1 to 1024. */
|
||||
|
||||
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 1. This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||
|
||||
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_FilterInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be transmitted. This parameter can be a value
|
||||
of @ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||
be transmitted. This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||
transmitted. This parameter can be a value between
|
||||
0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||
to 0xFF. */
|
||||
} CanTxMsg;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be received. This parameter can be a value of
|
||||
@ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||
0xFF. */
|
||||
|
||||
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||
the mailbox passes through. This parameter can be a
|
||||
value between 0 to 0xFF */
|
||||
} CanRxMsg;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
|
||||
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
|
||||
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANINITFAILED CAN_InitStatus_Failed
|
||||
#define CANINITOK CAN_InitStatus_Success
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
|
||||
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
|
||||
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
|
||||
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
|
||||
((MODE) == CAN_Mode_LoopBack)|| \
|
||||
((MODE) == CAN_Mode_Silent) || \
|
||||
((MODE) == CAN_Mode_Silent_LoopBack))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
|
||||
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
|
||||
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
|
||||
|
||||
|
||||
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
|
||||
((MODE) == CAN_OperatingMode_Normal)|| \
|
||||
((MODE) == CAN_OperatingMode_Sleep))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_operating_mode_status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
|
||||
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
|
||||
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
|
||||
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
|
||||
((MODE) == CAN_FilterMode_IdList))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
|
||||
((SCALE) == CAN_FilterScale_32bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
|
||||
((FIFO) == CAN_FilterFIFO1))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Start_bank_filter_for_slave_CAN
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
|
||||
((IDTYPE) == CAN_Id_Extended))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_ID_STD CAN_Id_Standard
|
||||
#define CAN_ID_EXT CAN_Id_Extended
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
|
||||
|
||||
/* Legacy defines */
|
||||
#define CAN_RTR_DATA CAN_RTR_Data
|
||||
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
|
||||
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
|
||||
an empty mailbox */
|
||||
/* Legacy defines */
|
||||
#define CANTXFAILED CAN_TxStatus_Failed
|
||||
#define CANTXOK CAN_TxStatus_Ok
|
||||
#define CANTXPENDING CAN_TxStatus_Pending
|
||||
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
|
||||
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||
#define CANSLEEPOK CAN_Sleep_Ok
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_wake_up_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
|
||||
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
|
||||
|
||||
/* Legacy defines */
|
||||
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup CAN_Error_Code_constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
|
||||
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
|
||||
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
|
||||
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
|
||||
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
|
||||
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
|
||||
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
|
||||
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
|
||||
CAN_GetFlagStatus() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
|
||||
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
|
||||
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
|
||||
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
|
||||
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
|
||||
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
|
||||
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
|
||||
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
|
||||
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
|
||||
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
|
||||
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
|
||||
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
|
||||
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_SLAK ))
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
|
||||
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
||||
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
|
||||
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
|
||||
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
|
||||
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
|
||||
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
|
||||
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
|
||||
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
|
||||
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
|
||||
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
|
||||
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
|
||||
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||
|
||||
|
||||
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the CAN configuration to the default reset state *****/
|
||||
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||
|
||||
/* CAN Frames Transmission functions ******************************************/
|
||||
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||
|
||||
/* CAN Frames Reception functions *********************************************/
|
||||
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||
|
||||
/* Operation modes functions **************************************************/
|
||||
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||
|
||||
/* CAN Bus Error management functions *****************************************/
|
||||
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_CAN_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
400
bootloader/system/include/stm32f3-stdperiph/stm32f30x_comp.h
Normal file
400
bootloader/system/include/stm32f3-stdperiph/stm32f30x_comp.h
Normal file
@ -0,0 +1,400 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the COMP firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_COMP_H
|
||||
#define __STM32F30x_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMP_InvertingInput */
|
||||
|
||||
uint32_t COMP_NonInvertingInput; /*!< Selects the non inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMP_NonInvertingInput */
|
||||
|
||||
uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
|
||||
This parameter can be a value of @ref COMP_Output */
|
||||
|
||||
uint32_t COMP_BlankingSrce; /*!< Selects the output blanking source of the comparator.
|
||||
This parameter can be a value of @ref COMP_BlankingSrce */
|
||||
|
||||
uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
|
||||
This parameter can be a value of @ref COMP_OutputPoloarity */
|
||||
|
||||
uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
|
||||
This parameter can be a value of @ref COMP_Hysteresis */
|
||||
|
||||
uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
|
||||
and allows to adjust the speed/consumption.
|
||||
This parameter can be a value of @ref COMP_Mode */
|
||||
|
||||
}COMP_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
|
||||
#define COMP_Selection_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Selection */
|
||||
#define COMP_Selection_COMP3 ((uint32_t)0x00000008) /*!< COMP3 Selection */
|
||||
#define COMP_Selection_COMP4 ((uint32_t)0x0000000C) /*!< COMP4 Selection */
|
||||
#define COMP_Selection_COMP5 ((uint32_t)0x00000010) /*!< COMP5 Selection */
|
||||
#define COMP_Selection_COMP6 ((uint32_t)0x00000014) /*!< COMP6 Selection */
|
||||
#define COMP_Selection_COMP7 ((uint32_t)0x00000018) /*!< COMP7 Selection */
|
||||
|
||||
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
|
||||
((PERIPH) == COMP_Selection_COMP2) || \
|
||||
((PERIPH) == COMP_Selection_COMP3) || \
|
||||
((PERIPH) == COMP_Selection_COMP4) || \
|
||||
((PERIPH) == COMP_Selection_COMP5) || \
|
||||
((PERIPH) == COMP_Selection_COMP6) || \
|
||||
((PERIPH) == COMP_Selection_COMP7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_DAC1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_OUT (PA4) connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_DAC2 ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_IO1 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
|
||||
PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
|
||||
PC0 for COMP7) connected to comparator inverting input */
|
||||
|
||||
#define COMP_InvertingInput_IO2 COMP_CSR_COMPxINSEL /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
|
||||
PB15 for COMP6) connected to comparator inverting input */
|
||||
|
||||
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC1) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC2) || \
|
||||
((INPUT) == COMP_InvertingInput_IO1) || \
|
||||
((INPUT) == COMP_InvertingInput_IO2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_NonInvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
|
||||
PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
|
||||
PA0 for COMP7) connected to comparator non inverting input */
|
||||
|
||||
#define COMP_NonInvertingInput_IO2 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
|
||||
PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
|
||||
|
||||
#define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_NonInvertingInput_IO1) || \
|
||||
((INPUT) == COMP_NonInvertingInput_IO2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
|
||||
|
||||
/* Output Redirection common for all comparators COMP1...COMP7 */
|
||||
#define COMP_Output_TIM1BKIN COMP_CSR_COMPxOUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
|
||||
#define COMP_Output_TIM1BKIN2 ((uint32_t)0x00000800) /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */
|
||||
#define COMP_Output_TIM8BKIN ((uint32_t)0x00000C00) /*!< COMP output connected to TIM8 Break Input (BKIN) */
|
||||
#define COMP_Output_TIM8BKIN2 ((uint32_t)0x00001000) /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */
|
||||
#define COMP_Output_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
|
||||
|
||||
/* Output Redirection common for COMP1 and COMP2 */
|
||||
#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00001800) /*!< COMP output connected to TIM1 OCREF Clear */
|
||||
#define COMP_Output_TIM1IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM1 Input Capture 1 */
|
||||
#define COMP_Output_TIM2IC4 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 4 */
|
||||
#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM2 OCREF Clear */
|
||||
#define COMP_Output_TIM3IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM3 Input Capture 1 */
|
||||
#define COMP_Output_TIM3OCREFCLR ((uint32_t)0x00002C00) /*!< COMP output connected to TIM3 OCREF Clear */
|
||||
|
||||
/* Output Redirection specific to COMP3 */
|
||||
#define COMP_Output_TIM4IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM4 Input Capture 1 */
|
||||
#define COMP_Output_TIM3IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM3 Input Capture 2 */
|
||||
#define COMP_Output_TIM15IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 Input Capture 1 */
|
||||
#define COMP_Output_TIM15BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM15 Break Input (BKIN) */
|
||||
|
||||
/* Output Redirection specific to COMP4 */
|
||||
#define COMP_Output_TIM3IC3 ((uint32_t)0x00001800) /*!< COMP output connected to TIM3 Input Capture 3 */
|
||||
#define COMP_Output_TIM8OCREFCLR ((uint32_t)0x00001C00) /*!< COMP output connected to TIM8 OCREF Clear */
|
||||
#define COMP_Output_TIM15IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM15 Input Capture 2 */
|
||||
#define COMP_Output_TIM4IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 2 */
|
||||
#define COMP_Output_TIM15OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 OCREF Clear */
|
||||
|
||||
/* Output Redirection specific to COMP5 */
|
||||
#define COMP_Output_TIM2IC1 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 1 */
|
||||
#define COMP_Output_TIM17IC1 ((uint32_t)0x00002000) /*!< COMP output connected to TIM17 Input Capture 1 */
|
||||
#define COMP_Output_TIM4IC3 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 3 */
|
||||
#define COMP_Output_TIM16BKIN ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Break Input (BKIN) */
|
||||
|
||||
/* Output Redirection specific to COMP6 */
|
||||
#define COMP_Output_TIM2IC2 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 2 */
|
||||
#define COMP_Output_COMP6TIM2OCREFCLR ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 OCREF Clear */
|
||||
#define COMP_Output_TIM16OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM16 OCREF Clear */
|
||||
#define COMP_Output_TIM16IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Input Capture 1 */
|
||||
#define COMP_Output_TIM4IC4 ((uint32_t)0x00002C00) /*!< COMP output connected to TIM4 Input Capture 4 */
|
||||
|
||||
/* Output Redirection specific to COMP7 */
|
||||
#define COMP_Output_TIM2IC3 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 3 */
|
||||
#define COMP_Output_TIM1IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM1 Input Capture 2 */
|
||||
#define COMP_Output_TIM17OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 OCREF Clear */
|
||||
#define COMP_Output_TIM17BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM16 Break Input (BKIN) */
|
||||
|
||||
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM1IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC4) || \
|
||||
((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_COMP6TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM3OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM8BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM8BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC2) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM15IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM15BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM8OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC3) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM15IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC3) || \
|
||||
((OUTPUT) == COMP_Output_TIM16BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM17IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC2) || \
|
||||
((OUTPUT) == COMP_Output_TIM16IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM4IC4) || \
|
||||
((OUTPUT) == COMP_Output_TIM16OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC3) || \
|
||||
((OUTPUT) == COMP_Output_TIM1IC2) || \
|
||||
((OUTPUT) == COMP_Output_TIM17BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM17OCREFCLR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_BlankingSrce
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* No blanking source can be selected for all comparators */
|
||||
#define COMP_BlankingSrce_None ((uint32_t)0x00000000) /*!< No blanking source */
|
||||
|
||||
/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
|
||||
#define COMP_BlankingSrce_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP1 and COMP2 */
|
||||
#define COMP_BlankingSrce_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP1, COMP2 and COMP5 */
|
||||
#define COMP_BlankingSrce_TIM3OC3 ((uint32_t)0x000C0000) /*!< TIM2 OC3 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP3 and COMP6 */
|
||||
#define COMP_BlankingSrce_TIM2OC4 ((uint32_t)0x000C0000) /*!< TIM2 OC4 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
|
||||
#define COMP_BlankingSrce_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source for COMP4 */
|
||||
#define COMP_BlankingSrce_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for compartor */
|
||||
#define COMP_BlankingSrce_TIM15OC1 ((uint32_t)0x000C0000) /*!< TIM15 OC1 selected as blanking source for compartor */
|
||||
|
||||
/* Blanking source common for COMP6 and COMP7 */
|
||||
#define COMP_BlankingSrce_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for compartor */
|
||||
|
||||
#define IS_COMP_BLANKING_SOURCE(SOURCE) (((SOURCE) == COMP_BlankingSrce_None) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM1OC5) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM2OC3) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM3OC3) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM2OC4) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM8OC5) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM3OC4) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM15OC1) || \
|
||||
((SOURCE) == COMP_BlankingSrce_TIM15OC2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPoloarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
|
||||
#define COMP_OutputPol_Inverted COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
|
||||
|
||||
#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
|
||||
((POL) == COMP_OutputPol_Inverted))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Hysteresis
|
||||
* @{
|
||||
*/
|
||||
/* Please refer to the electrical characteristics in the device datasheet for
|
||||
the hysteresis level */
|
||||
#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
|
||||
#define COMP_Hysteresis_Low COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
|
||||
#define COMP_Hysteresis_Medium COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
|
||||
#define COMP_Hysteresis_High COMP_CSR_COMPxHYST /*!< Hysteresis level high */
|
||||
|
||||
#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_Low) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_Medium) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Mode
|
||||
* @{
|
||||
*/
|
||||
/* Please refer to the electrical characteristics in the device datasheet for
|
||||
the power consumption values */
|
||||
#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
|
||||
#define COMP_Mode_MediumSpeed COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
|
||||
#define COMP_Mode_LowPower COMP_CSR_COMPxMODE_1 /*!< Low power mode */
|
||||
#define COMP_Mode_UltraLowPower COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
|
||||
|
||||
#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
|
||||
((MODE) == COMP_Mode_LowPower) || \
|
||||
((MODE) == COMP_Mode_MediumSpeed) || \
|
||||
((MODE) == COMP_Mode_HighSpeed))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel
|
||||
* @{
|
||||
*/
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the non-inverting input is at a higher voltage than the inverting input */
|
||||
#define COMP_OutputLevel_High COMP_CSR_COMPxOUT
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the non-inverting input is at a lower voltage than the inverting input*/
|
||||
#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_WindowMode
|
||||
* @{
|
||||
*/
|
||||
#define IS_COMP_WINDOW(WINDOW) (((WINDOW) == COMP_Selection_COMP2) || \
|
||||
((WINDOW) == COMP_Selection_COMP4) || \
|
||||
((WINDOW) == COMP_Selection_COMP6))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the COMP configuration to the default reset state ****/
|
||||
void COMP_DeInit(uint32_t COMP_Selection);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
|
||||
void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
|
||||
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
|
||||
|
||||
/* Window mode control function ***********************************************/
|
||||
void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
|
||||
/* COMP configuration locking function ****************************************/
|
||||
void COMP_LockConfig(uint32_t COMP_Selection);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_COMP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
121
bootloader/system/include/stm32f3-stdperiph/stm32f30x_crc.h
Normal file
121
bootloader/system/include/stm32f3-stdperiph/stm32f30x_crc.h
Normal file
@ -0,0 +1,121 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_CRC_H
|
||||
#define __STM32F30x_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!< Includes ----------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_ReverseInputData
|
||||
* @{
|
||||
*/
|
||||
#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
|
||||
#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
|
||||
#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
|
||||
#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
|
||||
|
||||
#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
|
||||
((DATA) == CRC_ReverseInputData_8bits) || \
|
||||
((DATA) == CRC_ReverseInputData_16bits) || \
|
||||
((DATA) == CRC_ReverseInputData_32bits))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_PolynomialSize
|
||||
* @{
|
||||
*/
|
||||
#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
|
||||
#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
|
||||
|
||||
#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
|
||||
((SIZE) == CRC_PolSize_8) || \
|
||||
((SIZE) == CRC_PolSize_16) || \
|
||||
((SIZE) == CRC_PolSize_32))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Configuration of the CRC computation unit **********************************/
|
||||
void CRC_DeInit(void);
|
||||
void CRC_ResetDR(void);
|
||||
void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize);
|
||||
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
|
||||
void CRC_ReverseOutputDataCmd(FunctionalState NewState);
|
||||
void CRC_SetInitRegister(uint32_t CRC_InitValue);
|
||||
void CRC_SetPolynomial(uint32_t CRC_Pol);
|
||||
|
||||
/* CRC computation ************************************************************/
|
||||
uint32_t CRC_CalcCRC(uint32_t CRC_Data);
|
||||
uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data);
|
||||
uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
|
||||
/* Independent register (IDR) access (write/read) *****************************/
|
||||
void CRC_SetIDRegister(uint8_t CRC_IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_CRC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
306
bootloader/system/include/stm32f3-stdperiph/stm32f30x_dac.h
Normal file
306
bootloader/system/include/stm32f3-stdperiph/stm32f30x_dac.h
Normal file
@ -0,0 +1,306 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_DAC_H
|
||||
#define __STM32F30x_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#define DAC_CR_DMAUDRIE ((uint32_t)0x00002000) /*!< DAC channel DMA underrun interrupt enable */
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||
((STATE) == DAC_OutputBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the DAC configuration to the default reset state *****/
|
||||
void DAC_DeInit(void);
|
||||
|
||||
/* DAC channels configuration: trigger, output buffer, data format functions */
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||
|
||||
/* DMA management functions ***************************************************/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_DAC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
108
bootloader/system/include/stm32f3-stdperiph/stm32f30x_dbgmcu.h
Normal file
108
bootloader/system/include/stm32f3-stdperiph/stm32f30x_dbgmcu.h
Normal file
@ -0,0 +1,108 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_DBGMCU_H
|
||||
#define __STM32F30x_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
|
||||
#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
|
||||
#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
|
||||
#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
|
||||
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
|
||||
#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
|
||||
|
||||
#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM15_STOP ((uint32_t)0x00000004)
|
||||
#define DBGMCU_TIM16_STOP ((uint32_t)0x00000008)
|
||||
#define DBGMCU_TIM17_STOP ((uint32_t)0x00000010)
|
||||
#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE0) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Device and Revision ID management functions ********************************/
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
|
||||
/* Peripherals Configuration functions ****************************************/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_DBGMCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
447
bootloader/system/include/stm32f3-stdperiph/stm32f30x_dma.h
Normal file
447
bootloader/system/include/stm32f3-stdperiph/stm32f30x_dma.h
Normal file
@ -0,0 +1,447 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30X_DMA_H
|
||||
#define __STM32F30X_DMA_H
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpadded"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
||||
((PERIPH) == DMA1_Channel2) || \
|
||||
((PERIPH) == DMA1_Channel3) || \
|
||||
((PERIPH) == DMA1_Channel4) || \
|
||||
((PERIPH) == DMA1_Channel5) || \
|
||||
((PERIPH) == DMA1_Channel6) || \
|
||||
((PERIPH) == DMA1_Channel7) || \
|
||||
((PERIPH) == DMA2_Channel1) || \
|
||||
((PERIPH) == DMA2_Channel2) || \
|
||||
((PERIPH) == DMA2_Channel3) || \
|
||||
((PERIPH) == DMA2_Channel4) || \
|
||||
((PERIPH) == DMA2_Channel5))
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
#define DMA_DIR_PeripheralDST DMA_CCR_DIR
|
||||
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
|
||||
((DIR) == DMA_DIR_PeripheralDST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralInc_Enable DMA_CCR_PINC
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
|
||||
((STATE) == DMA_PeripheralInc_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryInc_Enable DMA_CCR_MINC
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
|
||||
((STATE) == DMA_MemoryInc_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
|
||||
#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
|
||||
#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define DMA_Mode_Circular DMA_CCR_CIRC
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Priority_VeryHigh DMA_CCR_PL
|
||||
#define DMA_Priority_High DMA_CCR_PL_1
|
||||
#define DMA_Priority_Medium DMA_CCR_PL_0
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_to_memory
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_M2M_Enable DMA_CCR_MEM2MEM
|
||||
|
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
||||
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
||||
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
||||
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
||||
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
||||
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
||||
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
||||
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
||||
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
||||
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
||||
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
||||
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
||||
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
||||
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
||||
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
||||
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
||||
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
||||
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
||||
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
||||
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
||||
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
||||
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
||||
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
||||
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
||||
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
||||
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
||||
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
||||
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
||||
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the DMA configuration to the default reset state ******/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||
|
||||
/* Data Counter functions******************************************************/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30X_DMA_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
245
bootloader/system/include/stm32f3-stdperiph/stm32f30x_exti.h
Normal file
245
bootloader/system/include/stm32f3-stdperiph/stm32f30x_exti.h
Normal file
@ -0,0 +1,245 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the EXTI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_EXTI_H
|
||||
#define __STM32F30x_EXTI_H
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpadded"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTITrigger_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16
|
||||
Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17
|
||||
Connected to the RTC Alarm
|
||||
event */
|
||||
#define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18
|
||||
Connected to the USB Device
|
||||
Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19
|
||||
Connected to the RTC Tamper
|
||||
and Time Stamp events */
|
||||
#define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20
|
||||
Connected to the RTC wakeup
|
||||
event */
|
||||
#define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21
|
||||
Connected to the Comparator 1
|
||||
event */
|
||||
#define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22
|
||||
Connected to the Comparator 2
|
||||
event */
|
||||
#define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23
|
||||
Connected to the I2C1 wakeup
|
||||
event */
|
||||
#define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24
|
||||
Connected to the I2C2 wakeup
|
||||
event */
|
||||
#define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25
|
||||
Connected to the USART1 wakeup
|
||||
event */
|
||||
#define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26
|
||||
Connected to the USART2 wakeup
|
||||
event */
|
||||
#define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27
|
||||
reserved */
|
||||
#define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28
|
||||
Connected to the USART3 wakeup
|
||||
event */
|
||||
#define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29
|
||||
Connected to the Comparator 3
|
||||
event */
|
||||
#define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30
|
||||
Connected to the Comparator 4
|
||||
event */
|
||||
#define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31
|
||||
Connected to the Comparator 5
|
||||
event */
|
||||
#define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32
|
||||
Connected to the Comparator 6
|
||||
event */
|
||||
#define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33
|
||||
Connected to the Comparator 7
|
||||
event */
|
||||
#define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34
|
||||
Connected to the USART4 wakeup
|
||||
event */
|
||||
#define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35
|
||||
Connected to the USART5 wakeup
|
||||
event */
|
||||
|
||||
#define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23)
|
||||
#define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \
|
||||
((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)))
|
||||
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
|
||||
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
|
||||
((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \
|
||||
((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \
|
||||
((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the EXTI configuration to the default reset state *****/
|
||||
void EXTI_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_EXTI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
329
bootloader/system/include/stm32f3-stdperiph/stm32f30x_flash.h
Normal file
329
bootloader/system/include/stm32f3-stdperiph/stm32f30x_flash.h
Normal file
@ -0,0 +1,329 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_FLASH_H
|
||||
#define __STM32F30x_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_ERROR_PROGRAM,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
}FLASH_Status;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Flash_Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup FLASH_Address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_DATA_ADDRESS
|
||||
* @{
|
||||
*/
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
|
||||
#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
|
||||
#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
|
||||
#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
|
||||
#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
|
||||
#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
|
||||
#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
|
||||
#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
|
||||
#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
|
||||
#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
|
||||
#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
|
||||
#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
|
||||
#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
|
||||
#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
|
||||
#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
|
||||
#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
|
||||
#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
|
||||
#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
|
||||
#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
|
||||
#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
|
||||
#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
|
||||
#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
|
||||
#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
|
||||
#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
|
||||
#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
|
||||
#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
|
||||
#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
|
||||
#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
|
||||
#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
|
||||
#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
|
||||
#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
|
||||
#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
|
||||
|
||||
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Read_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read Protection Level
|
||||
*/
|
||||
#define OB_RDP_Level_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_Level_1 ((uint8_t)0xBB)
|
||||
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
|
||||
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
|
||||
((LEVEL) == OB_RDP_Level_1))/*||\
|
||||
((LEVEL) == OB_RDP_Level_2))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Option_Bytes_BOOT1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
|
||||
#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
|
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Option_Bytes_VDDA_Analog_Monitoring
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
|
||||
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
|
||||
|
||||
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
|
||||
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
|
||||
|
||||
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC3) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
|
||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup Timeout_definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* FLASH Interface configuration functions ************************************/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
|
||||
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
|
||||
|
||||
/* FLASH Memory Programming functions *****************************************/
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
|
||||
/* Option Bytes Programming functions *****************************************/
|
||||
void FLASH_OB_Unlock(void);
|
||||
void FLASH_OB_Lock(void);
|
||||
void FLASH_OB_Launch(void);
|
||||
FLASH_Status FLASH_OB_Erase(void);
|
||||
FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
|
||||
FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
|
||||
FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
|
||||
FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
|
||||
FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
|
||||
FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
|
||||
FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||
uint8_t FLASH_OB_GetUser(void);
|
||||
uint32_t FLASH_OB_GetWRP(void);
|
||||
FlagStatus FLASH_OB_GetRDP(void);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_FLASH_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
394
bootloader/system/include/stm32f3-stdperiph/stm32f30x_gpio.h
Normal file
394
bootloader/system/include/stm32f3-stdperiph/stm32f30x_gpio.h
Normal file
@ -0,0 +1,394 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the GPIO
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_GPIO_H
|
||||
#define __STM32F30x_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOD))
|
||||
/** @defgroup Configuration_Mode_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_type_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_Maximum_frequency_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
|
||||
GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
|
||||
GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
|
||||
}GPIOSpeed_TypeDef;
|
||||
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
|
||||
((SPEED) == GPIO_Speed_Level_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
|
||||
MCO, NJTRST, TRACED, TRACECK */
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15 */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
|
||||
USART1, USART2, USART3 */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
|
||||
COMP5_OUT, COMP6_OUT */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF_12 ((uint8_t)0x0E) /* TIM1 */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
|
||||
((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
|
||||
((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
|
||||
((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
|
||||
((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
|
||||
((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
|
||||
((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Speed_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
|
||||
#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
|
||||
#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the GPIO configuration to the default reset state *****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
|
||||
/* GPIO Alternate functions configuration functions ***************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_GPIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
477
bootloader/system/include/stm32f3-stdperiph/stm32f30x_i2c.h
Normal file
477
bootloader/system/include/stm32f3-stdperiph/stm32f30x_i2c.h
Normal file
@ -0,0 +1,477 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_I2C_H
|
||||
#define __STM32F30x_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization
|
||||
section in Reference manual*/
|
||||
|
||||
uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
|
||||
This parameter can be a value of @ref I2C_Analog_Filter */
|
||||
|
||||
uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
|
||||
This parameter can be a number between 0x00 and 0x0F */
|
||||
|
||||
uint32_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
|
||||
This parameter can be a 7-bit or 10-bit address */
|
||||
|
||||
uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
|
||||
((PERIPH) == I2C2))
|
||||
|
||||
/** @defgroup I2C_Analog_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
|
||||
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
|
||||
((FILTER) == I2C_AnalogFilter_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Digital_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Mode_I2C ((uint32_t)0x00000000)
|
||||
#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
|
||||
#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
|
||||
|
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Ack_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_Ack_Disable I2C_CR2_NACK
|
||||
|
||||
#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
|
||||
((ACK) == I2C_Ack_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
|
||||
#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
|
||||
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Direction_Transmitter ((uint16_t)0x0000)
|
||||
#define I2C_Direction_Receiver ((uint16_t)0x0400)
|
||||
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||
((DIRECTION) == I2C_Direction_Receiver))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
|
||||
#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
|
||||
|
||||
#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_slave_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_own_address2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address2_mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_OA2_NoMask ((uint8_t)0x00)
|
||||
#define I2C_OA2_Mask01 ((uint8_t)0x01)
|
||||
#define I2C_OA2_Mask02 ((uint8_t)0x02)
|
||||
#define I2C_OA2_Mask03 ((uint8_t)0x03)
|
||||
#define I2C_OA2_Mask04 ((uint8_t)0x04)
|
||||
#define I2C_OA2_Mask05 ((uint8_t)0x05)
|
||||
#define I2C_OA2_Mask06 ((uint8_t)0x06)
|
||||
#define I2C_OA2_Mask07 ((uint8_t)0x07)
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
|
||||
((MASK) == I2C_OA2_Mask01) || \
|
||||
((MASK) == I2C_OA2_Mask02) || \
|
||||
((MASK) == I2C_OA2_Mask03) || \
|
||||
((MASK) == I2C_OA2_Mask04) || \
|
||||
((MASK) == I2C_OA2_Mask05) || \
|
||||
((MASK) == I2C_OA2_Mask06) || \
|
||||
((MASK) == I2C_OA2_Mask07))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_timeout
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_TIMINGR ((uint8_t)0x10)
|
||||
#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
|
||||
#define I2C_Register_ISR ((uint8_t)0x18)
|
||||
#define I2C_Register_ICR ((uint8_t)0x1C)
|
||||
#define I2C_Register_PECR ((uint8_t)0x20)
|
||||
#define I2C_Register_RXDR ((uint8_t)0x24)
|
||||
#define I2C_Register_TXDR ((uint8_t)0x28)
|
||||
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_TIMINGR) || \
|
||||
((REGISTER) == I2C_Register_TIMEOUTR) || \
|
||||
((REGISTER) == I2C_Register_ISR) || \
|
||||
((REGISTER) == I2C_Register_ICR) || \
|
||||
((REGISTER) == I2C_Register_PECR) || \
|
||||
((REGISTER) == I2C_Register_RXDR) || \
|
||||
((REGISTER) == I2C_Register_TXDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_NACKF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
|
||||
((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
|
||||
((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
|
||||
((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
|
||||
((FLAG) == I2C_FLAG_BUSY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_TXIS I2C_ISR_TXIS
|
||||
#define I2C_IT_RXNE I2C_ISR_RXNE
|
||||
#define I2C_IT_ADDR I2C_ISR_ADDR
|
||||
#define I2C_IT_NACKF I2C_ISR_NACKF
|
||||
#define I2C_IT_STOPF I2C_ISR_STOPF
|
||||
#define I2C_IT_TC I2C_ISR_TC
|
||||
#define I2C_IT_TCR I2C_ISR_TCR
|
||||
#define I2C_IT_BERR I2C_ISR_BERR
|
||||
#define I2C_IT_ARLO I2C_ISR_ARLO
|
||||
#define I2C_IT_OVR I2C_ISR_OVR
|
||||
#define I2C_IT_PECERR I2C_ISR_PECERR
|
||||
#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_IT_ALERT I2C_ISR_ALERT
|
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
|
||||
((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
|
||||
((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
|
||||
((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||
((IT) == I2C_IT_ALERT))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ReloadEndMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Reload_Mode I2C_CR2_RELOAD
|
||||
#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
|
||||
#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
|
||||
|
||||
|
||||
#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
|
||||
((MODE) == I2C_AutoEnd_Mode) || \
|
||||
((MODE) == I2C_SoftEnd_Mode))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_StartStopMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_No_StartStop ((uint32_t)0x00000000)
|
||||
#define I2C_Generate_Stop I2C_CR2_STOP
|
||||
#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_Generate_Start_Write I2C_CR2_START
|
||||
|
||||
|
||||
#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
|
||||
((MODE) == I2C_Generate_Start_Read) || \
|
||||
((MODE) == I2C_Generate_Start_Write) || \
|
||||
((MODE) == I2C_No_StartStop))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
|
||||
void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* Communications handling functions ******************************************/
|
||||
void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
|
||||
void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
|
||||
uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
|
||||
void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
|
||||
|
||||
/* SMBUS management functions ************************************************/
|
||||
void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* I2C registers management functions *****************************************/
|
||||
uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||
|
||||
/* Data transfers management functions ****************************************/
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_I2C_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
153
bootloader/system/include/stm32f3-stdperiph/stm32f30x_iwdg.h
Normal file
153
bootloader/system/include/stm32f3-stdperiph/stm32f30x_iwdg.h
Normal file
@ -0,0 +1,153 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the IWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30X_IWDG_H
|
||||
#define __STM32F30X_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
|
||||
((ACCESS) == IWDG_WriteAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
|
||||
((PRESCALER) == IWDG_Prescaler_8) || \
|
||||
((PRESCALER) == IWDG_Prescaler_16) || \
|
||||
((PRESCALER) == IWDG_Prescaler_32) || \
|
||||
((PRESCALER) == IWDG_Prescaler_64) || \
|
||||
((PRESCALER) == IWDG_Prescaler_128)|| \
|
||||
((PRESCALER) == IWDG_Prescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||
#define IWDG_FLAG_WVU ((uint16_t)0x0002)
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
|
||||
((FLAG) == IWDG_FLAG_WVU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Reload_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_CounterWindow_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Prescaler and Counter configuration functions ******************************/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_SetWindowValue(uint16_t WindowValue);
|
||||
|
||||
/* IWDG activation function ***************************************************/
|
||||
void IWDG_Enable(void);
|
||||
|
||||
/* Flag management function ***************************************************/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30X_IWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
204
bootloader/system/include/stm32f3-stdperiph/stm32f30x_misc.h
Normal file
204
bootloader/system/include/stm32f3-stdperiph/stm32f30x_misc.h
Normal file
@ -0,0 +1,204 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_MISC_H
|
||||
#define __STM32F30x_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type (For
|
||||
the complete STM32 Devices IRQ Channels list, please
|
||||
refer to stm32f30x.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15.
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15.
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/**
|
||||
*
|
||||
@verbatim
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
============================================================================================================================
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_SysTick_clock_source
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
277
bootloader/system/include/stm32f3-stdperiph/stm32f30x_opamp.h
Normal file
277
bootloader/system/include/stm32f3-stdperiph/stm32f30x_opamp.h
Normal file
@ -0,0 +1,277 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_opamp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the operational
|
||||
* amplifiers (OPAMP) firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_OPAMP_H
|
||||
#define __STM32F30x_OPAMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief OPAMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t OPAMP_InvertingInput; /*!< Selects the inverting input of the operational amplifier.
|
||||
This parameter can be a value of @ref OPAMP_InvertingInput */
|
||||
|
||||
uint32_t OPAMP_NonInvertingInput; /*!< Selects the non inverting input of the operational amplifier.
|
||||
This parameter can be a value of @ref OPAMP_NonInvertingInput */
|
||||
|
||||
}OPAMP_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup OPAMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_Selection_OPAMP1 ((uint32_t)0x00000000) /*!< OPAMP1 Selection */
|
||||
#define OPAMP_Selection_OPAMP2 ((uint32_t)0x00000004) /*!< OPAMP2 Selection */
|
||||
#define OPAMP_Selection_OPAMP3 ((uint32_t)0x00000008) /*!< OPAMP3 Selection */
|
||||
#define OPAMP_Selection_OPAMP4 ((uint32_t)0x0000000C) /*!< OPAMP4 Selection */
|
||||
|
||||
#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
|
||||
((PERIPH) == OPAMP_Selection_OPAMP2) || \
|
||||
((PERIPH) == OPAMP_Selection_OPAMP3) || \
|
||||
((PERIPH) == OPAMP_Selection_OPAMP4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_InvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_InvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
|
||||
connected to OPAMPx inverting input */
|
||||
#define OPAMP_InvertingInput_IO2 OPAMP_CSR_VMSEL_0 /*!< IO2 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
|
||||
connected to OPAMPx inverting input */
|
||||
#define OPAMP_InvertingInput_PGA OPAMP_CSR_VMSEL_1 /*!< Resistor feedback output connected to OPAMPx inverting input (PGA mode) */
|
||||
#define OPAMP_InvertingInput_Vout OPAMP_CSR_VMSEL /*!< Vout connected to OPAMPx inverting input (follower mode) */
|
||||
|
||||
#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_InvertingInput_IO1) || \
|
||||
((INPUT) == OPAMP_InvertingInput_IO2) || \
|
||||
((INPUT) == OPAMP_InvertingInput_PGA) || \
|
||||
((INPUT) == OPAMP_InvertingInput_Vout))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_NonInvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_NonInvertingInput_IO2 OPAMP_CSR_VPSEL_0 /*!< IO2 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_NonInvertingInput_IO3 OPAMP_CSR_VPSEL_1 /*!< IO3 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
#define OPAMP_NonInvertingInput_IO4 OPAMP_CSR_VPSEL /*!< IO4 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
|
||||
connected to OPAMPx non inverting input */
|
||||
|
||||
#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NonInvertingInput_IO1) || \
|
||||
((INPUT) == OPAMP_NonInvertingInput_IO2) || \
|
||||
((INPUT) == OPAMP_NonInvertingInput_IO3) || \
|
||||
((INPUT) == OPAMP_NonInvertingInput_IO4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_PGAGain_Config
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_OPAMP_PGAGain_2 ((uint32_t)0x00000000)
|
||||
#define OPAMP_OPAMP_PGAGain_4 OPAMP_CSR_PGGAIN_0
|
||||
#define OPAMP_OPAMP_PGAGain_8 OPAMP_CSR_PGGAIN_1
|
||||
#define OPAMP_OPAMP_PGAGain_16 ((uint32_t)0x0000C000)
|
||||
|
||||
#define IS_OPAMP_PGAGAIN(GAIN) (((GAIN) == OPAMP_OPAMP_PGAGain_2) || \
|
||||
((GAIN) == OPAMP_OPAMP_PGAGain_4) || \
|
||||
((GAIN) == OPAMP_OPAMP_PGAGain_8) || \
|
||||
((GAIN) == OPAMP_OPAMP_PGAGain_16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_PGAConnect_Config
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_PGAConnect_No ((uint32_t)0x00000000)
|
||||
#define OPAMP_PGAConnect_IO1 OPAMP_CSR_PGGAIN_3
|
||||
#define OPAMP_PGAConnect_IO2 ((uint32_t)0x00030000)
|
||||
|
||||
#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGAConnect_No) || \
|
||||
((CONNECT) == OPAMP_PGAConnect_IO1) || \
|
||||
((CONNECT) == OPAMP_PGAConnect_IO2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_SecondaryInvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_OPAMP_SECONDARY_INVINPUT(INVINPUT) (((INVINPUT) == OPAMP_InvertingInput_IO1) || \
|
||||
((INVINPUT) == OPAMP_InvertingInput_IO2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Input
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_Input_Inverting ((uint32_t)0x00000018) /*!< Inverting input */
|
||||
#define OPAMP_Input_NonInverting ((uint32_t)0x00000013) /*!< Non inverting input */
|
||||
|
||||
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_Inverting) || \
|
||||
((INPUT) == OPAMP_Input_NonInverting))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Vref
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_Vref_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
|
||||
#define OPAMP_Vref_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
|
||||
#define OPAMP_Vref_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
|
||||
#define OPAMP_Vref_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
|
||||
|
||||
#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_Vref_3VDDA) || \
|
||||
((VREF) == OPAMP_Vref_10VDDA) || \
|
||||
((VREF) == OPAMP_Vref_50VDDA) || \
|
||||
((VREF) == OPAMP_Vref_90VDDA))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Trimming
|
||||
*/
|
||||
|
||||
#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
|
||||
#define OPAMP_Trimming_User OPAMP_CSR_USERTRIM /*!< User trimming */
|
||||
|
||||
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
|
||||
((TRIMMING) == OPAMP_Trimming_User))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_TrimValue
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_OutputLevel
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_OutputLevel_High OPAMP_CSR_OUTCAL
|
||||
#define OPAMP_OutputLevel_Low ((uint32_t)0x00000000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the OPAMP configuration to the default reset state ***/
|
||||
void OPAMP_DeInit(uint32_t OPAMP_Selection);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
|
||||
void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct);
|
||||
void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect);
|
||||
void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref);
|
||||
void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
|
||||
void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection);
|
||||
|
||||
/* Calibration functions ******************************************************/
|
||||
void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming);
|
||||
void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
|
||||
void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
|
||||
/* OPAMP configuration locking function ***************************************/
|
||||
void OPAMP_LockConfig(uint32_t OPAMP_Selection);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_OPAMP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
187
bootloader/system/include/stm32f3-stdperiph/stm32f30x_pwr.h
Normal file
187
bootloader/system/include/stm32f3-stdperiph/stm32f30x_pwr.h
Normal file
@ -0,0 +1,187 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_PWR_H
|
||||
#define __STM32F30x_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
|
||||
#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
|
||||
#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
|
||||
#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
|
||||
#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
|
||||
#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
|
||||
#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
|
||||
#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
|
||||
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
|
||||
((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
|
||||
((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_WakeUp_Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_WakeUpPin_1 PWR_CSR_EWUP1
|
||||
#define PWR_WakeUpPin_2 PWR_CSR_EWUP2
|
||||
#define PWR_WakeUpPin_3 PWR_CSR_EWUP3
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
|
||||
((PIN) == PWR_WakeUpPin_2) || \
|
||||
((PIN) == PWR_WakeUpPin_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||
#define PWR_Regulator_LowPower PWR_CR_LPSDSR
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
|
||||
((REGULATOR) == PWR_Regulator_LowPower))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
|
||||
|
||||
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
|
||||
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
|
||||
|
||||
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the PWR configuration to the default reset state ******/
|
||||
void PWR_DeInit(void);
|
||||
|
||||
/* Backup Domain Access function **********************************************/
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState);
|
||||
|
||||
/* PVD configuration functions ************************************************/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_PVDCmd(FunctionalState NewState);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/* Flags management functions *************************************************/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_PWR_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
630
bootloader/system/include/stm32f3-stdperiph/stm32f30x_rcc.h
Normal file
630
bootloader/system/include/stm32f3-stdperiph/stm32f30x_rcc.h
Normal file
@ -0,0 +1,630 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the RCC
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_RCC_H
|
||||
#define __STM32F30x_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency;
|
||||
uint32_t HCLK_Frequency;
|
||||
uint32_t PCLK1_Frequency;
|
||||
uint32_t PCLK2_Frequency;
|
||||
uint32_t ADC12CLK_Frequency;
|
||||
uint32_t ADC34CLK_Frequency;
|
||||
uint32_t I2C1CLK_Frequency;
|
||||
uint32_t I2C2CLK_Frequency;
|
||||
uint32_t TIM1CLK_Frequency;
|
||||
uint32_t TIM8CLK_Frequency;
|
||||
uint32_t USART1CLK_Frequency;
|
||||
uint32_t USART2CLK_Frequency;
|
||||
uint32_t USART3CLK_Frequency;
|
||||
uint32_t UART4CLK_Frequency;
|
||||
uint32_t UART5CLK_Frequency;
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_HSE_ON ((uint8_t)0x01)
|
||||
#define RCC_HSE_Bypass ((uint8_t)0x05)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
|
||||
#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
|
||||
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
|
||||
((SOURCE) == RCC_PLLSource_PREDIV1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Multiplication_Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
|
||||
#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
|
||||
#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
|
||||
#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
|
||||
#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
|
||||
#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
|
||||
#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
|
||||
#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
|
||||
#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
|
||||
#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
|
||||
#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
|
||||
#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
|
||||
#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
|
||||
#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
|
||||
#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
|
||||
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
|
||||
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
|
||||
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
|
||||
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
|
||||
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
|
||||
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
|
||||
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
|
||||
((MUL) == RCC_PLLMul_16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PREDIV1_division_factor
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
|
||||
#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
|
||||
#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
|
||||
#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
|
||||
#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
|
||||
#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
|
||||
#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
|
||||
#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
|
||||
#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
|
||||
#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
|
||||
#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
|
||||
#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
|
||||
#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
|
||||
#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
|
||||
#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
|
||||
#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
|
||||
|
||||
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
|
||||
#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
|
||||
#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
|
||||
#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
|
||||
#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
|
||||
#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
|
||||
#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
|
||||
#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
|
||||
#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
|
||||
#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
|
||||
#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_APB2_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
|
||||
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
|
||||
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
|
||||
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_ADC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ADC1 & ADC2 */
|
||||
#define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
|
||||
#define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
|
||||
#define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
|
||||
#define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
|
||||
#define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
|
||||
#define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
|
||||
#define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
|
||||
#define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
|
||||
#define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
|
||||
#define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
|
||||
#define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
|
||||
#define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
|
||||
|
||||
/* ADC3 & ADC4 */
|
||||
#define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
|
||||
#define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
|
||||
#define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
|
||||
#define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
|
||||
#define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
|
||||
#define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
|
||||
#define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
|
||||
#define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
|
||||
#define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
|
||||
#define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
|
||||
#define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
|
||||
#define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
|
||||
#define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
|
||||
|
||||
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
|
||||
((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
|
||||
((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_TIM_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
|
||||
#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
|
||||
|
||||
#define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
|
||||
#define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
|
||||
|
||||
#define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
|
||||
((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_I2C_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
|
||||
|
||||
#define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
|
||||
#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
|
||||
|
||||
#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
|
||||
((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_USART_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
|
||||
#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
|
||||
#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
|
||||
#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
|
||||
|
||||
#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
|
||||
#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
|
||||
#define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
|
||||
#define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
|
||||
|
||||
#define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
|
||||
#define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
|
||||
#define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
|
||||
#define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
|
||||
|
||||
#define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
|
||||
#define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
|
||||
#define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
|
||||
#define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
|
||||
|
||||
#define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
|
||||
#define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
|
||||
#define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
|
||||
#define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
|
||||
|
||||
#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
|
||||
((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
|
||||
((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
|
||||
((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
|
||||
((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
|
||||
|
||||
|
||||
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSE_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_LSE_ON RCC_BDCR_LSEON
|
||||
#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
|
||||
#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
|
||||
#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
|
||||
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
|
||||
#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
|
||||
|
||||
/** @defgroup RCC_LSE_Drive_Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
|
||||
#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
|
||||
#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
|
||||
#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
|
||||
#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
|
||||
((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
|
||||
#define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
|
||||
#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
|
||||
#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
|
||||
#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
|
||||
#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
|
||||
#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
|
||||
#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
|
||||
#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
|
||||
#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
|
||||
#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
|
||||
#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
|
||||
#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
|
||||
#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
|
||||
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
|
||||
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
|
||||
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
|
||||
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF887FE) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xCD0137C8) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MCOSource_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCOSource_LSI ((uint8_t)0x02)
|
||||
#define RCC_MCOSource_LSE ((uint8_t)0x03)
|
||||
#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCOSource_HSI ((uint8_t)0x05)
|
||||
#define RCC_MCOSource_HSE ((uint8_t)0x06)
|
||||
#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
|
||||
|
||||
#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
|
||||
((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
|
||||
((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
|
||||
((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_USB_Device_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
|
||||
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
|
||||
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x11)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
|
||||
#define RCC_FLAG_MCOF ((uint8_t)0x9C)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_OBLRST ((uint8_t)0x59)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x5A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x5B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
|
||||
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
|
||||
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
|
||||
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
|
||||
((FLAG) == RCC_FLAG_MCOF))
|
||||
|
||||
#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the RCC clock configuration to the default reset state */
|
||||
void RCC_DeInit(void);
|
||||
|
||||
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
|
||||
void RCC_HSEConfig(uint8_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_LSEConfig(uint32_t RCC_LSE);
|
||||
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCOConfig(uint8_t RCC_MCOSource);
|
||||
|
||||
/* System, AHB and APB busses clocks configuration functions ******************/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
|
||||
void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
|
||||
void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
|
||||
void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
|
||||
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
|
||||
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_RCC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
863
bootloader/system/include/stm32f3-stdperiph/stm32f30x_rtc.h
Normal file
863
bootloader/system/include/stm32f3-stdperiph/stm32f30x_rtc.h
Normal file
@ -0,0 +1,863 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_RTC_H
|
||||
#define __STM32F30x_RTC_H
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpadded"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief RTC Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x7F */
|
||||
|
||||
uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x1FFF */
|
||||
}RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be set to a value in the 0-12 range
|
||||
if the RTC_HourFormat_12 is selected or 0-23 range if
|
||||
the RTC_HourFormat_24 is selected. */
|
||||
|
||||
uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t RTC_Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be set to a value in the 1-31 range. */
|
||||
|
||||
uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be set to a value in the 0-99 range. */
|
||||
}RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
|
||||
|
||||
uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter
|
||||
must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this
|
||||
parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
}RTC_AlarmTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Hour_Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HourFormat_24 ((uint32_t)0x00000000)
|
||||
#define RTC_HourFormat_12 ((uint32_t)0x00000040)
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
|
||||
((FORMAT) == RTC_HourFormat_24))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Asynchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Synchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_H12_AM ((uint8_t)0x00)
|
||||
#define RTC_H12_PM ((uint8_t)0x40)
|
||||
#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Year_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Coded in BCD format */
|
||||
#define RTC_Month_January ((uint8_t)0x01)
|
||||
#define RTC_Month_February ((uint8_t)0x02)
|
||||
#define RTC_Month_March ((uint8_t)0x03)
|
||||
#define RTC_Month_April ((uint8_t)0x04)
|
||||
#define RTC_Month_May ((uint8_t)0x05)
|
||||
#define RTC_Month_June ((uint8_t)0x06)
|
||||
#define RTC_Month_July ((uint8_t)0x07)
|
||||
#define RTC_Month_August ((uint8_t)0x08)
|
||||
#define RTC_Month_September ((uint8_t)0x09)
|
||||
#define RTC_Month_October ((uint8_t)0x10)
|
||||
#define RTC_Month_November ((uint8_t)0x11)
|
||||
#define RTC_Month_December ((uint8_t)0x12)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_Weekday_Monday ((uint8_t)0x01)
|
||||
#define RTC_Weekday_Tuesday ((uint8_t)0x02)
|
||||
#define RTC_Weekday_Wednesday ((uint8_t)0x03)
|
||||
#define RTC_Weekday_Thursday ((uint8_t)0x04)
|
||||
#define RTC_Weekday_Friday ((uint8_t)0x05)
|
||||
#define RTC_Weekday_Saturday ((uint8_t)0x06)
|
||||
#define RTC_Weekday_Sunday ((uint8_t)0x07)
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Alarm_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
|
||||
((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmMask_None ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
|
||||
#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
|
||||
#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
|
||||
#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
|
||||
#define RTC_AlarmMask_All ((uint32_t)0x80808080)
|
||||
#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Alarm_A ((uint32_t)0x00000100)
|
||||
#define RTC_Alarm_B ((uint32_t)0x00000200)
|
||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
|
||||
#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Value
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Wakeup_Timer_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
|
||||
#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
|
||||
#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
|
||||
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
|
||||
#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Stamp_Edges_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
|
||||
#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
|
||||
#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
|
||||
((EDGE) == RTC_TimeStampEdge_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Output_Disable ((uint32_t)0x00000000)
|
||||
#define RTC_Output_AlarmA ((uint32_t)0x00200000)
|
||||
#define RTC_Output_AlarmB ((uint32_t)0x00400000)
|
||||
#define RTC_Output_WakeUp ((uint32_t)0x00600000)
|
||||
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
|
||||
((OUTPUT) == RTC_Output_AlarmA) || \
|
||||
((OUTPUT) == RTC_Output_AlarmB) || \
|
||||
((OUTPUT) == RTC_Output_WakeUp))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
|
||||
#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
|
||||
((POL) == RTC_OutputPolarity_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Digital_Calibration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
|
||||
#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
|
||||
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
|
||||
((SIGN) == RTC_CalibSign_Negative))
|
||||
#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Calib_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
|
||||
#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
|
||||
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
|
||||
((OUTPUT) == RTC_CalibOutput_1Hz))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_period_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 32s, else 2exp20 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 16s, else 2exp19 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 8s, else 2exp18 RTCCLK seconds */
|
||||
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_8sec))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
|
||||
during a X -second window = Y - CALM[8:0].
|
||||
with Y = 512, 256, 128 when X = 32, 16, 8 */
|
||||
#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
|
||||
during a 32-second window = CALM[8:0]. */
|
||||
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
|
||||
((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
|
||||
#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
|
||||
((SAVE) == RTC_DayLightSaving_ADD1H))
|
||||
|
||||
#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
|
||||
((OPERATION) == RTC_StoreOperation_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Trigger_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
|
||||
#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
|
||||
#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_HighLevel))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Filter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
|
||||
|
||||
#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
|
||||
consecutive samples at the active leve. */
|
||||
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
|
||||
((FILTER) == RTC_TamperFilter_2Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_4Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_8Sample))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 32768 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 16384 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 8192 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 4096 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 2048 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 1024 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 512 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 256 */
|
||||
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 1 RTCCLK cycle */
|
||||
#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 2 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 4 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 8 RTCCLK cycles */
|
||||
|
||||
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pins_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
|
||||
input tamper 1 */
|
||||
#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
|
||||
input tamper 2 */
|
||||
#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
|
||||
input tamper 3 */
|
||||
|
||||
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
|
||||
#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
|
||||
((TYPE) == RTC_OutputType_PushPull))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Add_1_Second_Parameter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
|
||||
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
|
||||
((SEL) == RTC_ShiftAdd1S_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Substract_Fraction_Of_Second_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Backup_Registers_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
|
||||
#define RTC_BKP_DR1 ((uint32_t)0x00000001)
|
||||
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
|
||||
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
|
||||
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
|
||||
#define RTC_BKP_DR5 ((uint32_t)0x00000005)
|
||||
#define RTC_BKP_DR6 ((uint32_t)0x00000006)
|
||||
#define RTC_BKP_DR7 ((uint32_t)0x00000007)
|
||||
#define RTC_BKP_DR8 ((uint32_t)0x00000008)
|
||||
#define RTC_BKP_DR9 ((uint32_t)0x00000009)
|
||||
#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
|
||||
#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
|
||||
#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
|
||||
#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
|
||||
#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
|
||||
#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
|
||||
#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
|
||||
((BKP) == RTC_BKP_DR1) || \
|
||||
((BKP) == RTC_BKP_DR2) || \
|
||||
((BKP) == RTC_BKP_DR3) || \
|
||||
((BKP) == RTC_BKP_DR4) || \
|
||||
((BKP) == RTC_BKP_DR5) || \
|
||||
((BKP) == RTC_BKP_DR6) || \
|
||||
((BKP) == RTC_BKP_DR7) || \
|
||||
((BKP) == RTC_BKP_DR8) || \
|
||||
((BKP) == RTC_BKP_DR9) || \
|
||||
((BKP) == RTC_BKP_DR10) || \
|
||||
((BKP) == RTC_BKP_DR11) || \
|
||||
((BKP) == RTC_BKP_DR12) || \
|
||||
((BKP) == RTC_BKP_DR13) || \
|
||||
((BKP) == RTC_BKP_DR14) || \
|
||||
((BKP) == RTC_BKP_DR15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Format_BIN ((uint32_t)0x000000000)
|
||||
#define RTC_Format_BCD ((uint32_t)0x000000001)
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
|
||||
#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
|
||||
#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
|
||||
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
|
||||
#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
|
||||
#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
|
||||
#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
|
||||
#define RTC_FLAG_INITF ((uint32_t)0x00000040)
|
||||
#define RTC_FLAG_RSF ((uint32_t)0x00000020)
|
||||
#define RTC_FLAG_INITS ((uint32_t)0x00000010)
|
||||
#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
|
||||
#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
|
||||
#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
|
||||
#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
|
||||
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
|
||||
((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
|
||||
((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
|
||||
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
|
||||
((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
|
||||
((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
|
||||
((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
|
||||
((FLAG) == RTC_FLAG_SHPF))
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS ((uint32_t)0x00008000)
|
||||
#define RTC_IT_WUT ((uint32_t)0x00004000)
|
||||
#define RTC_IT_ALRB ((uint32_t)0x00002000)
|
||||
#define RTC_IT_ALRA ((uint32_t)0x00001000)
|
||||
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
|
||||
#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
|
||||
#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
|
||||
|
||||
|
||||
#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
|
||||
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
|
||||
((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
|
||||
((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
|
||||
((IT) == RTC_IT_TAMP3))
|
||||
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the RTC configuration to the default reset state *****/
|
||||
ErrorStatus RTC_DeInit(void);
|
||||
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_WriteProtectionCmd(FunctionalState NewState);
|
||||
ErrorStatus RTC_EnterInitMode(void);
|
||||
void RTC_ExitInitMode(void);
|
||||
ErrorStatus RTC_WaitForSynchro(void);
|
||||
ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
|
||||
void RTC_BypassShadowCmd(FunctionalState NewState);
|
||||
|
||||
/* Time and Date configuration functions **************************************/
|
||||
ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
uint32_t RTC_GetSubSecond(void);
|
||||
ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
|
||||
/* Alarms (Alarm A and Alarm B) configuration functions **********************/
|
||||
void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
|
||||
void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
|
||||
uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
|
||||
|
||||
/* WakeUp Timer configuration functions ***************************************/
|
||||
void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
|
||||
void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
|
||||
uint32_t RTC_GetWakeUpCounter(void);
|
||||
ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Daylight Saving configuration functions ************************************/
|
||||
void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
|
||||
uint32_t RTC_GetStoreOperation(void);
|
||||
|
||||
/* Output pin Configuration function ******************************************/
|
||||
void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
|
||||
|
||||
/* Digital Calibration configuration functions ********************************/
|
||||
void RTC_CalibOutputCmd(FunctionalState NewState);
|
||||
void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
|
||||
ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
|
||||
uint32_t RTC_SmoothCalibPlusPulses,
|
||||
uint32_t RTC_SmouthCalibMinusPulsesValue);
|
||||
|
||||
/* TimeStamp configuration functions ******************************************/
|
||||
void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
|
||||
void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
|
||||
RTC_DateTypeDef* RTC_StampDateStruct);
|
||||
uint32_t RTC_GetTimeStampSubSecond(void);
|
||||
|
||||
/* Tampers configuration functions ********************************************/
|
||||
void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
|
||||
void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
|
||||
void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
|
||||
void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
|
||||
void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
|
||||
void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
|
||||
void RTC_TamperPullUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Backup Data Registers configuration functions ******************************/
|
||||
void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
|
||||
uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
|
||||
|
||||
/* Output Type Config configuration functions *********************************/
|
||||
void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
|
||||
|
||||
/* RTC_Shift_control_synchonisation_functions *********************************/
|
||||
ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
|
||||
FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
|
||||
void RTC_ClearFlag(uint32_t RTC_FLAG);
|
||||
ITStatus RTC_GetITStatus(uint32_t RTC_IT);
|
||||
void RTC_ClearITPendingBit(uint32_t RTC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_RTC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
617
bootloader/system/include/stm32f3-stdperiph/stm32f30x_spi.h
Normal file
617
bootloader/system/include/stm32f3-stdperiph/stm32f30x_spi.h
Normal file
@ -0,0 +1,617 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the SPI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_SPI_H
|
||||
#define __STM32F30x_SPI_H
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpadded"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief SPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||
}SPI_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2S_Mode */
|
||||
|
||||
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Standard */
|
||||
|
||||
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3) || \
|
||||
((PERIPH) == I2S2ext) || \
|
||||
((PERIPH) == I2S3ext))
|
||||
|
||||
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3) || \
|
||||
((PERIPH) == I2S2ext) || \
|
||||
((PERIPH) == I2S3ext))
|
||||
|
||||
#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
|
||||
((PERIPH) == I2S3ext))
|
||||
|
||||
/** @defgroup SPI_data_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
|
||||
((MODE) == SPI_Direction_2Lines_RxOnly) || \
|
||||
((MODE) == SPI_Direction_1Line_Rx) || \
|
||||
((MODE) == SPI_Direction_1Line_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
|
||||
((MODE) == SPI_Mode_Slave))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DataSize_4b ((uint16_t)0x0300)
|
||||
#define SPI_DataSize_5b ((uint16_t)0x0400)
|
||||
#define SPI_DataSize_6b ((uint16_t)0x0500)
|
||||
#define SPI_DataSize_7b ((uint16_t)0x0600)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0700)
|
||||
#define SPI_DataSize_9b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_10b ((uint16_t)0x0900)
|
||||
#define SPI_DataSize_11b ((uint16_t)0x0A00)
|
||||
#define SPI_DataSize_12b ((uint16_t)0x0B00)
|
||||
#define SPI_DataSize_13b ((uint16_t)0x0C00)
|
||||
#define SPI_DataSize_14b ((uint16_t)0x0D00)
|
||||
#define SPI_DataSize_15b ((uint16_t)0x0E00)
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0F00)
|
||||
#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
|
||||
((SIZE) == SPI_DataSize_5b) || \
|
||||
((SIZE) == SPI_DataSize_6b) || \
|
||||
((SIZE) == SPI_DataSize_7b) || \
|
||||
((SIZE) == SPI_DataSize_8b) || \
|
||||
((SIZE) == SPI_DataSize_9b) || \
|
||||
((SIZE) == SPI_DataSize_10b) || \
|
||||
((SIZE) == SPI_DataSize_11b) || \
|
||||
((SIZE) == SPI_DataSize_12b) || \
|
||||
((SIZE) == SPI_DataSize_13b) || \
|
||||
((SIZE) == SPI_DataSize_14b) || \
|
||||
((SIZE) == SPI_DataSize_15b) || \
|
||||
((SIZE) == SPI_DataSize_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRCLength_8b ((uint16_t)0x0000)
|
||||
#define SPI_CRCLength_16b ((uint16_t)0x0800)
|
||||
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
|
||||
((LENGTH) == SPI_CRCLength_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
|
||||
((CPOL) == SPI_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
|
||||
((CPHA) == SPI_CPHA_2Edge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||
((NSS) == SPI_NSS_Hard))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
|
||||
((BIT) == SPI_FirstBit_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
|
||||
((MODE) == I2S_Mode_SlaveRx) || \
|
||||
((MODE) == I2S_Mode_MasterTx)|| \
|
||||
((MODE) == I2S_Mode_MasterRx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
|
||||
((STANDARD) == I2S_Standard_MSB) || \
|
||||
((STANDARD) == I2S_Standard_LSB) || \
|
||||
((STANDARD) == I2S_Standard_PCMShort) || \
|
||||
((STANDARD) == I2S_Standard_PCMLong))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
|
||||
((FORMAT) == I2S_DataFormat_16bextended) || \
|
||||
((FORMAT) == I2S_DataFormat_24b) || \
|
||||
((FORMAT) == I2S_DataFormat_32b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
|
||||
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
|
||||
((OUTPUT) == I2S_MCLKOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
|
||||
((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||
((FREQ) == I2S_AudioFreq_Default))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||
#define I2S_CPOL_High ((uint16_t)0x0008)
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
|
||||
((CPOL) == I2S_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_FIFO_reception_threshold
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
|
||||
#define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000)
|
||||
#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
|
||||
((THRESHOLD) == SPI_RxFIFOThreshold_QF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||
#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_last_DMA_transfers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
|
||||
#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
|
||||
#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
|
||||
#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
|
||||
#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup SPI_NSS_internal_software_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
|
||||
((INTERNAL) == SPI_NSSInternalSoft_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Transmit_Receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_direction_transmit_receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
|
||||
((DIRECTION) == SPI_Direction_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
|
||||
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_RXNE) || \
|
||||
((IT) == SPI_I2S_IT_ERR))
|
||||
|
||||
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_I2S_IT_FRE ((uint8_t)0x58)
|
||||
|
||||
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
|
||||
((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_transmission_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
|
||||
#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
|
||||
#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
|
||||
#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_reception_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
|
||||
#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
|
||||
#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
|
||||
#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_I2S_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||
#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
|
||||
|
||||
|
||||
|
||||
#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
|
||||
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
|
||||
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
|
||||
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
|
||||
((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
|
||||
((FLAG) == I2S_FLAG_UDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_polynomial
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the SPI configuration to the default reset state*******/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
|
||||
void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
|
||||
uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Hardware CRC Calculation functions *****************************************/
|
||||
void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||
void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
// [ILG]
|
||||
#if defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_SPI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
301
bootloader/system/include/stm32f3-stdperiph/stm32f30x_syscfg.h
Normal file
301
bootloader/system/include/stm32f3-stdperiph/stm32f30x_syscfg.h
Normal file
@ -0,0 +1,301 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_syscfg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the SYSCFG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*!< Define to prevent recursive inclusion -----------------------------------*/
|
||||
#ifndef __STM32F30x_SYSCFG_H
|
||||
#define __STM32F30x_SYSCFG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!< Includes ----------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SYSCFG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
|
||||
#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
|
||||
#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
|
||||
|
||||
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PinSource0 ((uint8_t)0x00)
|
||||
#define EXTI_PinSource1 ((uint8_t)0x01)
|
||||
#define EXTI_PinSource2 ((uint8_t)0x02)
|
||||
#define EXTI_PinSource3 ((uint8_t)0x03)
|
||||
#define EXTI_PinSource4 ((uint8_t)0x04)
|
||||
#define EXTI_PinSource5 ((uint8_t)0x05)
|
||||
#define EXTI_PinSource6 ((uint8_t)0x06)
|
||||
#define EXTI_PinSource7 ((uint8_t)0x07)
|
||||
#define EXTI_PinSource8 ((uint8_t)0x08)
|
||||
#define EXTI_PinSource9 ((uint8_t)0x09)
|
||||
#define EXTI_PinSource10 ((uint8_t)0x0A)
|
||||
#define EXTI_PinSource11 ((uint8_t)0x0B)
|
||||
#define EXTI_PinSource12 ((uint8_t)0x0C)
|
||||
#define EXTI_PinSource13 ((uint8_t)0x0D)
|
||||
#define EXTI_PinSource14 ((uint8_t)0x0E)
|
||||
#define EXTI_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
|
||||
((PINSOURCE) == EXTI_PinSource1) || \
|
||||
((PINSOURCE) == EXTI_PinSource2) || \
|
||||
((PINSOURCE) == EXTI_PinSource3) || \
|
||||
((PINSOURCE) == EXTI_PinSource4) || \
|
||||
((PINSOURCE) == EXTI_PinSource5) || \
|
||||
((PINSOURCE) == EXTI_PinSource6) || \
|
||||
((PINSOURCE) == EXTI_PinSource7) || \
|
||||
((PINSOURCE) == EXTI_PinSource8) || \
|
||||
((PINSOURCE) == EXTI_PinSource9) || \
|
||||
((PINSOURCE) == EXTI_PinSource10) || \
|
||||
((PINSOURCE) == EXTI_PinSource11) || \
|
||||
((PINSOURCE) == EXTI_PinSource12) || \
|
||||
((PINSOURCE) == EXTI_PinSource13) || \
|
||||
((PINSOURCE) == EXTI_PinSource14) || \
|
||||
((PINSOURCE) == EXTI_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Memory_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
|
||||
#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
|
||||
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
|
||||
|
||||
|
||||
#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SRAM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_DMA_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /*!< Remap TIM17 DMA requests from channel1 to channel2 */
|
||||
#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /*!< Remap TIM16 DMA requests from channel3 to channel4 */
|
||||
#define SYSCFG_DMARemap_TIM6DAC1 SYSCFG_CFGR1_TIM6DAC1_DMA_RMP /*!< Remap TIM6/DAC1 DMA requests from DMA2 channel3 to DMA1 channel3 */
|
||||
#define SYSCFG_DMARemap_TIM7DAC2 SYSCFG_CFGR1_TIM7DAC2_DMA_RMP /*!< Remap TIM7/DAC2 DMA requests from DMA2 channel4 to DMA1 channel4 */
|
||||
#define SYSCFG_DMARemap_ADC2ADC4 SYSCFG_CFGR1_ADC24_DMA_RMP /*!< Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4 */
|
||||
|
||||
#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
|
||||
((REMAP) == SYSCFG_DMARemap_TIM16) || \
|
||||
((REMAP) == SYSCFG_DMARemap_TIM6DAC1) || \
|
||||
((REMAP) == SYSCFG_DMARemap_TIM7DAC2) || \
|
||||
((REMAP) == SYSCFG_DMARemap_ADC2ADC4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Trigger_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_TriggerRemap_DACTIM3 SYSCFG_CFGR1_DAC_TRIG_RMP /*!< Remap DAC trigger to TIM3 */
|
||||
#define SYSCFG_TriggerRemap_TIM1TIM17 SYSCFG_CFGR1_TIM1_ITR3_RMP /*!< Remap TIM1 ITR3 to TIM17 OC */
|
||||
|
||||
#define IS_SYSCFG_TRIGGER_REMAP(REMAP) (((REMAP) == SYSCFG_TriggerRemap_DACTIM3) || \
|
||||
((REMAP) == SYSCFG_TriggerRemap_TIM1TIM17))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_EncoderRemap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_EncoderRemap_No ((uint32_t)0x00000000) /*!< No redirection */
|
||||
#define SYSCFG_EncoderRemap_TIM2 SYSCFG_CFGR1_ENCODER_MODE_0 /*!< Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2 */
|
||||
#define SYSCFG_EncoderRemap_TIM3 SYSCFG_CFGR1_ENCODER_MODE_1 /*!< Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2 */
|
||||
#define SYSCFG_EncoderRemap_TIM4 SYSCFG_CFGR1_ENCODER_MODE /*!< Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2 */
|
||||
|
||||
#define IS_SYSCFG_ENCODER_REMAP(REMAP) (((REMAP) == SYSCFG_EncoderRemap_No) || \
|
||||
((REMAP) == SYSCFG_EncoderRemap_TIM2) || \
|
||||
((REMAP) == SYSCFG_EncoderRemap_TIM3) || \
|
||||
((REMAP) == SYSCFG_EncoderRemap_TIM4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_I2C_FastModePlus_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
|
||||
#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_I2C2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_FPU_Interrupt_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_IT_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Inexact Interrupt enable (interrupt disabled by default) */
|
||||
#define SYSCFG_IT_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Input denormal Interrupt enable */
|
||||
#define SYSCFG_IT_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Overflow Interrupt enable */
|
||||
#define SYSCFG_IT_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Underflow Interrupt enable */
|
||||
#define SYSCFG_IT_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Divide-by-zero Interrupt enable */
|
||||
#define SYSCFG_IT_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Invalid operation Interrupt enable */
|
||||
|
||||
#define IS_SYSCFG_IT(IT) ((((IT) & (uint32_t)0x03FFFFFF) == 0) && ((IT) != 0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Lock_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
|
||||
#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
|
||||
#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
|
||||
|
||||
#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
|
||||
((CONFIG) == SYSCFG_Break_SRAMParity) || \
|
||||
((CONFIG) == SYSCFG_Break_Lockup))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_SRAMWRP_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_SRAMWRP_Page0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
|
||||
#define SYSCFG_SRAMWRP_Page1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
|
||||
#define SYSCFG_SRAMWRP_Page2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
|
||||
#define SYSCFG_SRAMWRP_Page3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
|
||||
#define SYSCFG_SRAMWRP_Page4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
|
||||
#define SYSCFG_SRAMWRP_Page5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
|
||||
#define SYSCFG_SRAMWRP_Page6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
|
||||
#define SYSCFG_SRAMWRP_Page7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
|
||||
|
||||
#define IS_SYSCFG_PAGE(PAGE)((((PAGE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((PAGE) != 0x00000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
|
||||
|
||||
#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the SYSCFG configuration to the default reset state **/
|
||||
void SYSCFG_DeInit(void);
|
||||
|
||||
/* SYSCFG configuration functions *********************************************/
|
||||
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
|
||||
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
|
||||
void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState);
|
||||
void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap);
|
||||
void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState);
|
||||
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
|
||||
void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState);
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
|
||||
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
|
||||
void SYSCFG_BypassParityCheckDisable(void);
|
||||
void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP);
|
||||
FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
|
||||
void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F30x_SYSCFG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1345
bootloader/system/include/stm32f3-stdperiph/stm32f30x_tim.h
Normal file
1345
bootloader/system/include/stm32f3-stdperiph/stm32f30x_tim.h
Normal file
File diff suppressed because it is too large
Load Diff
607
bootloader/system/include/stm32f3-stdperiph/stm32f30x_usart.h
Normal file
607
bootloader/system/include/stm32f3-stdperiph/stm32f30x_usart.h
Normal file
@ -0,0 +1,607 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the USART
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30x_USART_H
|
||||
#define __STM32F30x_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint32_t USART_Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control*/
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4) || \
|
||||
((PERIPH) == UART5))
|
||||
|
||||
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3))
|
||||
|
||||
#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4))
|
||||
|
||||
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WordLength_8b ((uint32_t)0x00000000)
|
||||
#define USART_WordLength_9b USART_CR1_M
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||
((LENGTH) == USART_WordLength_9b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_StopBits_1 ((uint32_t)0x00000000)
|
||||
#define USART_StopBits_2 USART_CR2_STOP_1
|
||||
#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||
((STOPBITS) == USART_StopBits_2) || \
|
||||
((STOPBITS) == USART_StopBits_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Parity_No ((uint32_t)0x00000000)
|
||||
#define USART_Parity_Even USART_CR1_PCE
|
||||
#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||
((PARITY) == USART_Parity_Even) || \
|
||||
((PARITY) == USART_Parity_Odd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Mode_Rx USART_CR1_RE
|
||||
#define USART_Mode_Tx USART_CR1_TE
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
|
||||
((MODE) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
|
||||
#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
|
||||
#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
|
||||
#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Clock_Disable ((uint32_t)0x00000000)
|
||||
#define USART_Clock_Enable USART_CR2_CLKEN
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||
((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPOL_Low ((uint32_t)0x00000000)
|
||||
#define USART_CPOL_High USART_CR2_CPOL
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPHA_1Edge ((uint32_t)0x00000000)
|
||||
#define USART_CPHA_2Edge USART_CR2_CPHA
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LastBit_Disable ((uint32_t)0x00000000)
|
||||
#define USART_LastBit_Enable USART_CR2_LBCL
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAReq_Tx USART_CR3_DMAT
|
||||
#define USART_DMAReq_Rx USART_CR3_DMAR
|
||||
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
|
||||
((DMAREQ) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Recception_Error
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
|
||||
#define USART_DMAOnError_Disable USART_CR3_DDRE
|
||||
#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
|
||||
((DMAERROR) == USART_DMAOnError_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_MuteMode_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
|
||||
#define USART_WakeUp_AddressMark USART_CR1_WAKE
|
||||
#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Address_Detection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_AddressLength_4b ((uint32_t)0x00000000)
|
||||
#define USART_AddressLength_7b USART_CR2_ADDM7
|
||||
#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
|
||||
((ADDRESS) == USART_AddressLength_7b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_StopMode_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
|
||||
#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
|
||||
#define USART_WakeUpSource_RXNE (uint32_t)(USART_CR3_WUS_0 | USART_CR3_WUS_1)
|
||||
#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
|
||||
((SOURCE) == USART_WakeUpSource_StartBit) || \
|
||||
((SOURCE) == USART_WakeUpSource_RXNE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
|
||||
#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IrDAMode_LowPower USART_CR3_IRLP
|
||||
#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||
((MODE) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DE_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DEPolarity_High ((uint32_t)0x00000000)
|
||||
#define USART_DEPolarity_Low USART_CR3_DEP
|
||||
#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
|
||||
((POLARITY) == USART_DEPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Inversion_Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_InvPin_Tx USART_CR2_TXINV
|
||||
#define USART_InvPin_Rx USART_CR2_RXINV
|
||||
#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
|
||||
((PIN) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_AutoBaudRate_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
|
||||
#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
|
||||
#define USART_AutoBaudRate_0x7FFrame USART_CR2_ABRMODE_1
|
||||
#define USART_AutoBaudRate_0x55Frame (USART_CR2_ABRMODE_0 | USART_CR2_ABRMODE_1)
|
||||
#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
|
||||
((MODE) == USART_AutoBaudRate_FallingEdge) || \
|
||||
((MODE) == USART_AutoBaudRate_0x7FFrame) || \
|
||||
((MODE) == USART_AutoBaudRate_0x55Frame))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_OVR_DETECTION
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
|
||||
#define USART_OVRDetection_Disable USART_CR3_OVRDIS
|
||||
#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
|
||||
((OVR) == USART_OVRDetection_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup USART_Request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Request_ABRRQ USART_RQR_ABRRQ
|
||||
#define USART_Request_SBKRQ USART_RQR_SBKRQ
|
||||
#define USART_Request_MMRQ USART_RQR_MMRQ
|
||||
#define USART_Request_RXFRQ USART_RQR_RXFRQ
|
||||
#define USART_Request_TXFRQ USART_RQR_TXFRQ
|
||||
|
||||
#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
|
||||
((REQUEST) == USART_Request_RXFRQ) || \
|
||||
((REQUEST) == USART_Request_MMRQ) || \
|
||||
((REQUEST) == USART_Request_SBKRQ) || \
|
||||
((REQUEST) == USART_Request_ABRRQ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
#define USART_FLAG_REACK USART_ISR_REACK
|
||||
#define USART_FLAG_TEACK USART_ISR_TEACK
|
||||
#define USART_FLAG_WU USART_ISR_WUF
|
||||
#define USART_FLAG_RWU USART_ISR_RWU
|
||||
#define USART_FLAG_SBK USART_ISR_SBKF
|
||||
#define USART_FLAG_CM USART_ISR_CMF
|
||||
#define USART_FLAG_BUSY USART_ISR_BUSY
|
||||
#define USART_FLAG_ABRF USART_ISR_ABRF
|
||||
#define USART_FLAG_ABRE USART_ISR_ABRE
|
||||
#define USART_FLAG_EOB USART_ISR_EOBF
|
||||
#define USART_FLAG_RTO USART_ISR_RTOF
|
||||
#define USART_FLAG_nCTSS USART_ISR_CTS
|
||||
#define USART_FLAG_CTS USART_ISR_CTSIF
|
||||
#define USART_FLAG_LBD USART_ISR_LBD
|
||||
#define USART_FLAG_TXE USART_ISR_TXE
|
||||
#define USART_FLAG_TC USART_ISR_TC
|
||||
#define USART_FLAG_RXNE USART_ISR_RXNE
|
||||
#define USART_FLAG_IDLE USART_ISR_IDLE
|
||||
#define USART_FLAG_ORE USART_ISR_ORE
|
||||
#define USART_FLAG_NE USART_ISR_NE
|
||||
#define USART_FLAG_FE USART_ISR_FE
|
||||
#define USART_FLAG_PE USART_ISR_PE
|
||||
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
|
||||
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
|
||||
((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
|
||||
((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
|
||||
((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
|
||||
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
|
||||
((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
|
||||
((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
|
||||
((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
|
||||
((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
|
||||
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition
|
||||
* @brief USART Interrupt definition
|
||||
* USART_IT possible values
|
||||
* Elements values convention: 0xZZZZYYXX
|
||||
* XX: Position of the corresponding Interrupt
|
||||
* YY: Register index
|
||||
* ZZZZ: Flag position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_WU ((uint32_t)0x00140316)
|
||||
#define USART_IT_CM ((uint32_t)0x0011010E)
|
||||
#define USART_IT_EOB ((uint32_t)0x000C011B)
|
||||
#define USART_IT_RTO ((uint32_t)0x000B011A)
|
||||
#define USART_IT_PE ((uint32_t)0x00000108)
|
||||
#define USART_IT_TXE ((uint32_t)0x00070107)
|
||||
#define USART_IT_TC ((uint32_t)0x00060106)
|
||||
#define USART_IT_RXNE ((uint32_t)0x00050105)
|
||||
#define USART_IT_IDLE ((uint32_t)0x00040104)
|
||||
#define USART_IT_LBD ((uint32_t)0x00080206)
|
||||
#define USART_IT_CTS ((uint32_t)0x0009030A)
|
||||
#define USART_IT_ERR ((uint32_t)0x00000300)
|
||||
#define USART_IT_ORE ((uint32_t)0x00030300)
|
||||
#define USART_IT_NE ((uint32_t)0x00020300)
|
||||
#define USART_IT_FE ((uint32_t)0x00010300)
|
||||
|
||||
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
|
||||
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
|
||||
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
|
||||
((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
|
||||
((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
|
||||
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Global_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
|
||||
#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
|
||||
#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
|
||||
#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
|
||||
void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
|
||||
|
||||
/* STOP Mode functions ********************************************************/
|
||||
void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
|
||||
|
||||
/* AutoBaudRate functions *****************************************************/
|
||||
void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||
|
||||
/* Multi-Processor Communication functions ************************************/
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
|
||||
void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
|
||||
/* LIN mode functions *********************************************************/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Half-duplex mode function **************************************************/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Smartcard mode functions ***************************************************/
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
|
||||
void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
|
||||
|
||||
/* IrDA mode functions ********************************************************/
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* RS485 mode functions *******************************************************/
|
||||
void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
|
||||
void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
|
||||
void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
|
||||
void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
|
||||
void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
|
||||
void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30x_USART_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
109
bootloader/system/include/stm32f3-stdperiph/stm32f30x_wwdg.h
Normal file
109
bootloader/system/include/stm32f3-stdperiph/stm32f30x_wwdg.h
Normal file
@ -0,0 +1,109 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file contains all the functions prototypes for the WWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F30X_WWDG_H
|
||||
#define __STM32F30X_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
|
||||
((PRESCALER) == WWDG_Prescaler_2) || \
|
||||
((PRESCALER) == WWDG_Prescaler_4) || \
|
||||
((PRESCALER) == WWDG_Prescaler_8))
|
||||
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the WWDG configuration to the default reset state ****/
|
||||
void WWDG_DeInit(void);
|
||||
|
||||
/* Prescaler, Refresh window and Counter configuration functions **************/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
|
||||
/* WWDG activation functions **************************************************/
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F30X_WWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
10
bootloader/system/src/cmsis/README_DEVICE_30x.txt
Normal file
10
bootloader/system/src/cmsis/README_DEVICE_30x.txt
Normal file
@ -0,0 +1,10 @@
|
||||
The system_stm32f30x.c file is from stsw-stm32108.zip,
|
||||
the folder:
|
||||
|
||||
STM32F30x_DSP_StdPeriph_Lib_V1.0.0/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates
|
||||
|
||||
The vectors_stm32f30x.c file was created to conform with the assembly files
|
||||
gc_ride7/startup_stm3230x.s.
|
||||
|
||||
|
||||
STM32F37x_DSP_StdPeriph_Lib_V1.0.0/Libraries/CMSIS/Device/ST/STM32F37x/Include
|
||||
382
bootloader/system/src/cmsis/system_stm32f30x.c
Normal file
382
bootloader/system/src/cmsis/system_stm32f30x.c
Normal file
@ -0,0 +1,382 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f30x.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 04-September-2012
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F30x devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* stm32f30x_Clock_Configuration_V1.0.0.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f30x.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f30x.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* Supported STM32F30x device
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | PLL (HSE)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 72000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 72000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency(Hz) | 8000000
|
||||
*----------------------------------------------------------------------------
|
||||
* PLLMUL | 9
|
||||
*-----------------------------------------------------------------------------
|
||||
* PREDIV | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* USB Clock | DISABLE
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency(WS) | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* Prefetch Buffer | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f30x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f30x.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t SystemCoreClock = 72000000;
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F30x_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR &= 0xF87FC00C;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
|
||||
RCC->CFGR &= (uint32_t)0xFF80FFFF;
|
||||
|
||||
/* Reset PREDIV1[3:0] bits */
|
||||
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
|
||||
|
||||
/* Reset USARTSW[1:0], I2CSW and TIMs bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
SetSysClock();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
|
||||
* 8 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock */
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
|
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */
|
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
}
|
||||
break;
|
||||
default: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
|
||||
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Enable Prefetch Buffer and set Flash Latency */
|
||||
FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 1 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
/* PCLK1 = HCLK / 2 */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
||||
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
297
bootloader/system/src/cmsis/vectors_stm32f30x.c
Normal file
297
bootloader/system/src/cmsis/vectors_stm32f30x.c
Normal file
@ -0,0 +1,297 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include "cortexm/ExceptionHandlers.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
void __attribute__((weak))
|
||||
Default_Handler(void);
|
||||
|
||||
// Forward declaration of the specific IRQ handlers. These are aliased
|
||||
// to the Default_Handler, which is a 'forever' loop. When the application
|
||||
// defines a handler (with the same name), this will automatically take
|
||||
// precedence over these weak definitions
|
||||
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
WWDG_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
PVD_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TAMPER_STAMP_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
RTC_WKUP_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
FLASH_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
RCC_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
EXTI0_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
EXTI1_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
EXTI2_TS_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
EXTI3_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
EXTI4_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA1_Channel1_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA1_Channel2_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA1_Channel3_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA1_Channel4_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA1_Channel5_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA1_Channel6_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA1_Channel7_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
ADC1_2_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
USB_HP_CAN1_TX_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
USB_LP_CAN1_RX0_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
CAN1_RX1_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
CAN1_SCE_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
EXTI9_5_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM1_BRK_TIM15_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM1_UP_TIM16_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM1_TRG_COM_TIM17_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM1_CC_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM2_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM3_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM4_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
I2C1_EV_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
I2C1_ER_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
I2C2_EV_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
I2C2_ER_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
SPI1_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
SPI2_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
USART1_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
USART2_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
USART3_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
EXTI15_10_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
RTC_Alarm_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
USBWakeUp_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM8_BRK_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM8_UP_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM8_TRG_COM_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM8_CC_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
ADC3_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
SPI3_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
UART4_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
UART5_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM6_DAC_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
TIM7_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA2_Channel1_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA2_Channel2_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA2_Channel3_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA2_Channel4_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
DMA2_Channel5_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
ADC4_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
COMP1_2_3_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
COMP4_5_6_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
COMP7_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
USB_HP_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
USB_LP_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
USBWakeUp_RMP_IRQHandler(void);
|
||||
void __attribute__ ((weak, alias ("Default_Handler")))
|
||||
FPU_IRQHandler(void);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
extern unsigned int _estack;
|
||||
|
||||
typedef void
|
||||
(* const pHandler)(void);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// The vector table.
|
||||
// This relies on the linker script to place at correct location in memory.
|
||||
|
||||
__attribute__ ((section(".isr_vector"),used))
|
||||
pHandler __isr_vectors[] =
|
||||
{
|
||||
// Core Level - CM4
|
||||
(pHandler) &_estack, // The initial stack pointer
|
||||
Reset_Handler, // The reset handler
|
||||
|
||||
NMI_Handler, // The NMI handler
|
||||
HardFault_Handler, // The hard fault handler
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
MemManage_Handler, // The MPU fault handler
|
||||
BusFault_Handler, // The bus fault handler
|
||||
UsageFault_Handler, // The usage fault handler
|
||||
#else
|
||||
0, 0, 0, // Reserved
|
||||
#endif
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
SVC_Handler, // SVCall handler
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
DebugMon_Handler, // Debug monitor handler
|
||||
#else
|
||||
0, // Reserved
|
||||
#endif
|
||||
0, // Reserved
|
||||
PendSV_Handler, // The PendSV handler
|
||||
SysTick_Handler, // The SysTick handler
|
||||
|
||||
// ----------------------------------------------------------------------
|
||||
// Chip Level - STM32F30x
|
||||
WWDG_IRQHandler, //
|
||||
PVD_IRQHandler, //
|
||||
TAMPER_STAMP_IRQHandler, //
|
||||
RTC_WKUP_IRQHandler, //
|
||||
FLASH_IRQHandler, //
|
||||
RCC_IRQHandler, //
|
||||
EXTI0_IRQHandler, //
|
||||
EXTI1_IRQHandler, //
|
||||
EXTI2_TS_IRQHandler, //
|
||||
EXTI3_IRQHandler, //
|
||||
EXTI4_IRQHandler, //
|
||||
DMA1_Channel1_IRQHandler, //
|
||||
DMA1_Channel2_IRQHandler, //
|
||||
DMA1_Channel3_IRQHandler, //
|
||||
DMA1_Channel4_IRQHandler, //
|
||||
DMA1_Channel5_IRQHandler, //
|
||||
DMA1_Channel6_IRQHandler, //
|
||||
DMA1_Channel7_IRQHandler, //
|
||||
ADC1_2_IRQHandler, //
|
||||
USB_HP_CAN1_TX_IRQHandler, //
|
||||
USB_LP_CAN1_RX0_IRQHandler, //
|
||||
CAN1_RX1_IRQHandler, //
|
||||
CAN1_SCE_IRQHandler, //
|
||||
EXTI9_5_IRQHandler, //
|
||||
TIM1_BRK_TIM15_IRQHandler, //
|
||||
TIM1_UP_TIM16_IRQHandler, //
|
||||
TIM1_TRG_COM_TIM17_IRQHandler, //
|
||||
TIM1_CC_IRQHandler, //
|
||||
TIM2_IRQHandler, //
|
||||
TIM3_IRQHandler, //
|
||||
TIM4_IRQHandler, //
|
||||
I2C1_EV_IRQHandler, //
|
||||
I2C1_ER_IRQHandler, //
|
||||
I2C2_EV_IRQHandler, //
|
||||
I2C2_ER_IRQHandler, //
|
||||
SPI1_IRQHandler, //
|
||||
SPI2_IRQHandler, //
|
||||
USART1_IRQHandler, //
|
||||
USART2_IRQHandler, //
|
||||
USART3_IRQHandler, //
|
||||
EXTI15_10_IRQHandler, //
|
||||
RTC_Alarm_IRQHandler, //
|
||||
USBWakeUp_IRQHandler, //
|
||||
TIM8_BRK_IRQHandler, //
|
||||
TIM8_UP_IRQHandler, //
|
||||
TIM8_TRG_COM_IRQHandler, //
|
||||
TIM8_CC_IRQHandler, //
|
||||
ADC3_IRQHandler, //
|
||||
0, //
|
||||
0, //
|
||||
0, //
|
||||
SPI3_IRQHandler, //
|
||||
UART4_IRQHandler, //
|
||||
UART5_IRQHandler, //
|
||||
TIM6_DAC_IRQHandler, //
|
||||
TIM7_IRQHandler, //
|
||||
DMA2_Channel1_IRQHandler, //
|
||||
DMA2_Channel2_IRQHandler, //
|
||||
DMA2_Channel3_IRQHandler, //
|
||||
DMA2_Channel4_IRQHandler, //
|
||||
DMA2_Channel5_IRQHandler, //
|
||||
ADC4_IRQHandler, //
|
||||
0, //
|
||||
0, //
|
||||
COMP1_2_3_IRQHandler, //
|
||||
COMP4_5_6_IRQHandler, //
|
||||
COMP7_IRQHandler, //
|
||||
0, //
|
||||
0, //
|
||||
0, //
|
||||
0, //
|
||||
0, //
|
||||
0, //
|
||||
0, //
|
||||
USB_HP_IRQHandler, //
|
||||
USB_LP_IRQHandler, //
|
||||
USBWakeUp_RMP_IRQHandler, //
|
||||
0, //
|
||||
0, //
|
||||
0, //
|
||||
0, //
|
||||
FPU_IRQHandler //
|
||||
};
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// Processor ends up here if an unexpected interrupt occurs or a specific
|
||||
// handler is not present in the application code.
|
||||
|
||||
void __attribute__ ((section(".after_vectors")))
|
||||
Default_Handler(void)
|
||||
{
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
87
bootloader/system/src/cortexm/_initialize_hardware.c
Normal file
87
bootloader/system/src/cortexm/_initialize_hardware.c
Normal file
@ -0,0 +1,87 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include "cmsis_device.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
extern unsigned int __vectors_start;
|
||||
|
||||
// Forward declarations.
|
||||
|
||||
void
|
||||
__initialize_hardware_early(void);
|
||||
|
||||
void
|
||||
__initialize_hardware(void);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// This is the early hardware initialisation routine, it can be
|
||||
// redefined in the application for more complex cases that
|
||||
// require early inits (before BSS init).
|
||||
//
|
||||
// Called early from _start(), right before data & bss init.
|
||||
//
|
||||
// After Reset the Cortex-M processor is in Thread mode,
|
||||
// priority is Privileged, and the Stack is set to Main.
|
||||
|
||||
void
|
||||
__attribute__((weak))
|
||||
__initialize_hardware_early(void)
|
||||
{
|
||||
// Call the CSMSIS system initialisation routine.
|
||||
SystemInit();
|
||||
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
// Set VTOR to the actual address, provided by the linker script.
|
||||
// Override the manual, possibly wrong, SystemInit() setting.
|
||||
SCB->VTOR = (uint32_t)(&__vectors_start);
|
||||
#endif
|
||||
|
||||
// The current version of SystemInit() leaves the value of the clock
|
||||
// in a RAM variable (SystemCoreClock), which will be cleared shortly,
|
||||
// so it needs to be recomputed after the RAM initialisations
|
||||
// are completed.
|
||||
|
||||
#if defined(OS_INCLUDE_STARTUP_INIT_FP) || (defined (__VFP_FP__) && !defined (__SOFTFP__))
|
||||
|
||||
// Normally FP init is done by SystemInit(). In case this is not done
|
||||
// there, it is possible to force its inclusion by defining
|
||||
// OS_INCLUDE_STARTUP_INIT_FP.
|
||||
|
||||
// Enable the Cortex-M4 FPU only when -mfloat-abi=hard.
|
||||
// Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
|
||||
|
||||
// Set bits 20-23 to enable CP10 and CP11 coprocessor
|
||||
SCB->CPACR |= (0xF << 20);
|
||||
|
||||
#endif // (__VFP_FP__) && !(__SOFTFP__)
|
||||
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
// This is the second hardware initialisation routine, it can be
|
||||
// redefined in the application for more complex cases that
|
||||
// require custom inits (before constructors), otherwise these can
|
||||
// be done in main().
|
||||
//
|
||||
// Called from _start(), right after data & bss init, before
|
||||
// constructors.
|
||||
|
||||
void
|
||||
__attribute__((weak))
|
||||
__initialize_hardware(void)
|
||||
{
|
||||
// Call the CSMSIS system clock routine to store the clock frequency
|
||||
// in the SystemCoreClock global RAM location.
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
37
bootloader/system/src/cortexm/_reset_hardware.c
Normal file
37
bootloader/system/src/cortexm/_reset_hardware.c
Normal file
@ -0,0 +1,37 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include "cmsis_device.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
extern void
|
||||
__attribute__((noreturn))
|
||||
NVIC_SystemReset(void);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// Forward declarations
|
||||
|
||||
void
|
||||
__reset_hardware(void);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// This is the default hardware reset routine; it can be
|
||||
// redefined in the application for more complex applications.
|
||||
//
|
||||
// Called from _exit().
|
||||
|
||||
void
|
||||
__attribute__((weak,noreturn))
|
||||
__reset_hardware()
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
599
bootloader/system/src/cortexm/exception_handlers.c
Normal file
599
bootloader/system/src/cortexm/exception_handlers.c
Normal file
@ -0,0 +1,599 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include "cortexm/ExceptionHandlers.h"
|
||||
#include "cmsis_device.h"
|
||||
#include "arm/semihosting.h"
|
||||
#include "diag/Trace.h"
|
||||
#include <string.h>
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
extern void
|
||||
__attribute__((noreturn,weak))
|
||||
_start (void);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Default exception handlers. Override the ones here by defining your own
|
||||
// handler routines in your application code.
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(DEBUG)
|
||||
|
||||
// The DEBUG version is not naked, but has a proper stack frame,
|
||||
// to allow setting breakpoints at Reset_Handler.
|
||||
void __attribute__ ((section(".after_vectors"),noreturn))
|
||||
Reset_Handler (void)
|
||||
{
|
||||
_start ();
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
// The Release version is optimised to a quick branch to _start.
|
||||
void __attribute__ ((section(".after_vectors"),naked))
|
||||
Reset_Handler(void)
|
||||
{
|
||||
asm volatile
|
||||
(
|
||||
" ldr r0,=_start \n"
|
||||
" bx r0"
|
||||
:
|
||||
:
|
||||
:
|
||||
);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak))
|
||||
NMI_Handler (void)
|
||||
{
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(TRACE)
|
||||
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
// The values of BFAR and MMFAR stay unchanged if the BFARVALID or
|
||||
// MMARVALID is set. However, if a new fault occurs during the
|
||||
// execution of this fault handler, the value of the BFAR and MMFAR
|
||||
// could potentially be erased. In order to ensure the fault addresses
|
||||
// accessed are valid, the following procedure should be used:
|
||||
// 1. Read BFAR/MMFAR.
|
||||
// 2. Read CFSR to get BFARVALID or MMARVALID. If the value is 0, the
|
||||
// value of BFAR or MMFAR accessed can be invalid and can be discarded.
|
||||
// 3. Optionally clear BFARVALID or MMARVALID.
|
||||
// (See Joseph Yiu's book).
|
||||
|
||||
void
|
||||
dumpExceptionStack (ExceptionStackFrame* frame,
|
||||
uint32_t cfsr, uint32_t mmfar, uint32_t bfar,
|
||||
uint32_t lr)
|
||||
{
|
||||
trace_printf ("Stack frame:\n");
|
||||
trace_printf (" R0 = %08X\n", frame->r0);
|
||||
trace_printf (" R1 = %08X\n", frame->r1);
|
||||
trace_printf (" R2 = %08X\n", frame->r2);
|
||||
trace_printf (" R3 = %08X\n", frame->r3);
|
||||
trace_printf (" R12 = %08X\n", frame->r12);
|
||||
trace_printf (" LR = %08X\n", frame->lr);
|
||||
trace_printf (" PC = %08X\n", frame->pc);
|
||||
trace_printf (" PSR = %08X\n", frame->psr);
|
||||
trace_printf ("FSR/FAR:\n");
|
||||
trace_printf (" CFSR = %08X\n", cfsr);
|
||||
trace_printf (" HFSR = %08X\n", SCB->HFSR);
|
||||
trace_printf (" DFSR = %08X\n", SCB->DFSR);
|
||||
trace_printf (" AFSR = %08X\n", SCB->AFSR);
|
||||
|
||||
if (cfsr & (1UL << 7))
|
||||
{
|
||||
trace_printf (" MMFAR = %08X\n", mmfar);
|
||||
}
|
||||
if (cfsr & (1UL << 15))
|
||||
{
|
||||
trace_printf (" BFAR = %08X\n", bfar);
|
||||
}
|
||||
trace_printf ("Misc\n");
|
||||
trace_printf (" LR/EXC_RETURN= %08X\n", lr);
|
||||
}
|
||||
|
||||
#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
#if defined(__ARM_ARCH_6M__)
|
||||
|
||||
void
|
||||
dumpExceptionStack (ExceptionStackFrame* frame, uint32_t lr)
|
||||
{
|
||||
trace_printf ("Stack frame:\n");
|
||||
trace_printf (" R0 = %08X\n", frame->r0);
|
||||
trace_printf (" R1 = %08X\n", frame->r1);
|
||||
trace_printf (" R2 = %08X\n", frame->r2);
|
||||
trace_printf (" R3 = %08X\n", frame->r3);
|
||||
trace_printf (" R12 = %08X\n", frame->r12);
|
||||
trace_printf (" LR = %08X\n", frame->lr);
|
||||
trace_printf (" PC = %08X\n", frame->pc);
|
||||
trace_printf (" PSR = %08X\n", frame->psr);
|
||||
trace_printf ("Misc\n");
|
||||
trace_printf (" LR/EXC_RETURN= %08X\n", lr);
|
||||
}
|
||||
|
||||
#endif // defined(__ARM_ARCH_6M__)
|
||||
|
||||
#endif // defined(TRACE)
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
|
||||
|
||||
int
|
||||
isSemihosting (ExceptionStackFrame* frame, uint16_t opCode);
|
||||
|
||||
/**
|
||||
* This function provides the minimum functionality to make a semihosting program execute even without the debugger present.
|
||||
* @param frame pointer to an exception stack frame.
|
||||
* @param opCode the 16-bin word of the BKPT instruction.
|
||||
* @return 1 if the instruction was a valid semihosting call; 0 otherwise.
|
||||
*/
|
||||
int
|
||||
isSemihosting (ExceptionStackFrame* frame, uint16_t opCode)
|
||||
{
|
||||
uint16_t* pw = (uint16_t*) frame->pc;
|
||||
if (*pw == opCode)
|
||||
{
|
||||
uint32_t r0 = frame->r0;
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS) || defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
|
||||
uint32_t r1 = frame->r1;
|
||||
#endif
|
||||
#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
|
||||
uint32_t* blk = (uint32_t*) r1;
|
||||
#endif
|
||||
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
// trace_printf ("sh r0=%d\n", r0);
|
||||
#endif
|
||||
|
||||
switch (r0)
|
||||
{
|
||||
|
||||
#if defined(OS_USE_SEMIHOSTING)
|
||||
|
||||
case SEMIHOSTING_SYS_CLOCK:
|
||||
case SEMIHOSTING_SYS_ELAPSED:
|
||||
case SEMIHOSTING_SYS_FLEN:
|
||||
case SEMIHOSTING_SYS_GET_CMDLINE:
|
||||
case SEMIHOSTING_SYS_REMOVE:
|
||||
case SEMIHOSTING_SYS_RENAME:
|
||||
case SEMIHOSTING_SYS_SEEK:
|
||||
case SEMIHOSTING_SYS_SYSTEM:
|
||||
case SEMIHOSTING_SYS_TICKFREQ:
|
||||
case SEMIHOSTING_SYS_TMPNAM:
|
||||
case SEMIHOSTING_SYS_ISTTY:
|
||||
frame->r0 = (uint32_t)-1; // the call is not successful or not supported
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_SYS_CLOSE:
|
||||
frame->r0 = 0; // call is successful
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_SYS_ERRNO:
|
||||
frame->r0 = 0; // the value of the C library errno variable.
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_SYS_HEAPINFO:
|
||||
blk[0] = 0; // heap_base
|
||||
blk[1] = 0; // heap_limit
|
||||
blk[2] = 0; // stack_base
|
||||
blk[3] = 0; // stack_limit
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_SYS_ISERROR:
|
||||
frame->r0 = 0; // 0 if the status word is not an error indication
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_SYS_READ:
|
||||
// If R0 contains the same value as word 3, the call has
|
||||
// failed and EOF is assumed.
|
||||
frame->r0 = blk[2];
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_SYS_READC:
|
||||
frame->r0 = '\0'; // the byte read from the console.
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_SYS_TIME:
|
||||
frame->r0 = 0; // the number of seconds since 00:00 January 1, 1970.
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_ReportException:
|
||||
|
||||
NVIC_SystemReset ();
|
||||
// Should not reach here
|
||||
return 0;
|
||||
|
||||
#endif // defined(OS_USE_SEMIHOSTING)
|
||||
|
||||
#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
|
||||
|
||||
#define HANDLER_STDIN (1)
|
||||
#define HANDLER_STDOUT (2)
|
||||
#define HANDLER_STDERR (3)
|
||||
|
||||
case SEMIHOSTING_SYS_OPEN:
|
||||
// Process only standard io/out/err and return 1/2/3
|
||||
if (strcmp ((char*) blk[0], ":tt") == 0)
|
||||
{
|
||||
if ((blk[1] == 0))
|
||||
{
|
||||
frame->r0 = HANDLER_STDIN;
|
||||
break;
|
||||
}
|
||||
else if (blk[1] == 4)
|
||||
{
|
||||
frame->r0 = HANDLER_STDOUT;
|
||||
break;
|
||||
}
|
||||
else if (blk[1] == 8)
|
||||
{
|
||||
frame->r0 = HANDLER_STDERR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
frame->r0 = (uint32_t)-1; // the call is not successful or not supported
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_SYS_WRITE:
|
||||
// Silently ignore writes to stdout/stderr, fail on all other handler.
|
||||
if ((blk[0] == HANDLER_STDOUT) || (blk[0] == HANDLER_STDERR))
|
||||
{
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
frame->r0 = (uint32_t) blk[2]
|
||||
- trace_write ((char*) blk[1], blk[2]);
|
||||
#else
|
||||
frame->r0 = 0; // all sent, no more.
|
||||
#endif // defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
}
|
||||
else
|
||||
{
|
||||
// If other handler, return the total number of bytes
|
||||
// as the number of bytes that are not written.
|
||||
frame->r0 = blk[2];
|
||||
}
|
||||
break;
|
||||
|
||||
#endif // defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
|
||||
|
||||
#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
|
||||
|
||||
case SEMIHOSTING_SYS_WRITEC:
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
{
|
||||
char ch = *((char*) r1);
|
||||
trace_write (&ch, 1);
|
||||
}
|
||||
#endif
|
||||
// Register R0 is corrupted.
|
||||
break;
|
||||
|
||||
case SEMIHOSTING_SYS_WRITE0:
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
{
|
||||
char* p = ((char*) r1);
|
||||
trace_write (p, strlen (p));
|
||||
}
|
||||
#endif
|
||||
// Register R0 is corrupted.
|
||||
break;
|
||||
|
||||
#endif
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Alter the PC to make the exception returns to
|
||||
// the instruction after the faulty BKPT.
|
||||
frame->pc += 2;
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
// Hard Fault handler wrapper in assembly.
|
||||
// It extracts the location of stack frame and passes it to handler
|
||||
// in C as a pointer. We also pass the LR value as second
|
||||
// parameter.
|
||||
// (Based on Joseph Yiu's, The Definitive Guide to ARM Cortex-M3 and
|
||||
// Cortex-M4 Processors, Third Edition, Chap. 12.8, page 402).
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak,naked))
|
||||
HardFault_Handler (void)
|
||||
{
|
||||
asm volatile(
|
||||
" tst lr,#4 \n"
|
||||
" ite eq \n"
|
||||
" mrseq r0,msp \n"
|
||||
" mrsne r0,psp \n"
|
||||
" mov r1,lr \n"
|
||||
" ldr r2,=HardFault_Handler_C \n"
|
||||
" bx r2"
|
||||
|
||||
: /* Outputs */
|
||||
: /* Inputs */
|
||||
: /* Clobbers */
|
||||
);
|
||||
}
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak,used))
|
||||
HardFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)),
|
||||
uint32_t lr __attribute__((unused)))
|
||||
{
|
||||
#if defined(TRACE)
|
||||
uint32_t mmfar = SCB->MMFAR; // MemManage Fault Address
|
||||
uint32_t bfar = SCB->BFAR; // Bus Fault Address
|
||||
uint32_t cfsr = SCB->CFSR; // Configurable Fault Status Registers
|
||||
#endif
|
||||
|
||||
#if defined(OS_USE_SEMIHOSTING) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
|
||||
|
||||
// If the BKPT instruction is executed with C_DEBUGEN == 0 and MON_EN == 0,
|
||||
// it will cause the processor to enter a HardFault exception, with DEBUGEVT
|
||||
// in the Hard Fault Status register (HFSR) set to 1, and BKPT in the
|
||||
// Debug Fault Status register (DFSR) also set to 1.
|
||||
|
||||
if (((SCB->DFSR & SCB_DFSR_BKPT_Msk) != 0)
|
||||
&& ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0))
|
||||
{
|
||||
if (isSemihosting (frame, 0xBE00 + (AngelSWI & 0xFF)))
|
||||
{
|
||||
// Clear the exception cause in exception status.
|
||||
SCB->HFSR = SCB_HFSR_DEBUGEVT_Msk;
|
||||
|
||||
// Continue after the BKPT
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(TRACE)
|
||||
trace_printf ("[HardFault]\n");
|
||||
dumpExceptionStack (frame, cfsr, mmfar, bfar, lr);
|
||||
#endif // defined(TRACE)
|
||||
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__)
|
||||
|
||||
// Hard Fault handler wrapper in assembly.
|
||||
// It extracts the location of stack frame and passes it to handler
|
||||
// in C as a pointer. We also pass the LR value as second
|
||||
// parameter.
|
||||
// (Based on Joseph Yiu's, The Definitive Guide to ARM Cortex-M0
|
||||
// First Edition, Chap. 12.8, page 402).
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak,naked))
|
||||
HardFault_Handler (void)
|
||||
{
|
||||
asm volatile(
|
||||
" movs r0,#4 \n"
|
||||
" mov r1,lr \n"
|
||||
" tst r0,r1 \n"
|
||||
" beq 1f \n"
|
||||
" mrs r0,psp \n"
|
||||
" b 2f \n"
|
||||
"1: \n"
|
||||
" mrs r0,msp \n"
|
||||
"2:"
|
||||
" mov r1,lr \n"
|
||||
" ldr r2,=HardFault_Handler_C \n"
|
||||
" bx r2"
|
||||
|
||||
: /* Outputs */
|
||||
: /* Inputs */
|
||||
: /* Clobbers */
|
||||
);
|
||||
}
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak,used))
|
||||
HardFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)),
|
||||
uint32_t lr __attribute__((unused)))
|
||||
{
|
||||
// There is no semihosting support for Cortex-M0, since on ARMv6-M
|
||||
// faults are fatal and it is not possible to return from the handler.
|
||||
|
||||
#if defined(TRACE)
|
||||
trace_printf ("[HardFault]\n");
|
||||
dumpExceptionStack (frame, lr);
|
||||
#endif // defined(TRACE)
|
||||
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#endif // defined(__ARM_ARCH_6M__)
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak))
|
||||
MemManage_Handler (void)
|
||||
{
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak,naked))
|
||||
BusFault_Handler (void)
|
||||
{
|
||||
asm volatile(
|
||||
" tst lr,#4 \n"
|
||||
" ite eq \n"
|
||||
" mrseq r0,msp \n"
|
||||
" mrsne r0,psp \n"
|
||||
" mov r1,lr \n"
|
||||
" ldr r2,=BusFault_Handler_C \n"
|
||||
" bx r2"
|
||||
|
||||
: /* Outputs */
|
||||
: /* Inputs */
|
||||
: /* Clobbers */
|
||||
);
|
||||
}
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak,used))
|
||||
BusFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)),
|
||||
uint32_t lr __attribute__((unused)))
|
||||
{
|
||||
#if defined(TRACE)
|
||||
uint32_t mmfar = SCB->MMFAR; // MemManage Fault Address
|
||||
uint32_t bfar = SCB->BFAR; // Bus Fault Address
|
||||
uint32_t cfsr = SCB->CFSR; // Configurable Fault Status Registers
|
||||
|
||||
trace_printf ("[BusFault]\n");
|
||||
dumpExceptionStack (frame, cfsr, mmfar, bfar, lr);
|
||||
#endif // defined(TRACE)
|
||||
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak,naked))
|
||||
UsageFault_Handler (void)
|
||||
{
|
||||
asm volatile(
|
||||
" tst lr,#4 \n"
|
||||
" ite eq \n"
|
||||
" mrseq r0,msp \n"
|
||||
" mrsne r0,psp \n"
|
||||
" mov r1,lr \n"
|
||||
" ldr r2,=UsageFault_Handler_C \n"
|
||||
" bx r2"
|
||||
|
||||
: /* Outputs */
|
||||
: /* Inputs */
|
||||
: /* Clobbers */
|
||||
);
|
||||
}
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak,used))
|
||||
UsageFault_Handler_C (ExceptionStackFrame* frame __attribute__((unused)),
|
||||
uint32_t lr __attribute__((unused)))
|
||||
{
|
||||
#if defined(TRACE)
|
||||
uint32_t mmfar = SCB->MMFAR; // MemManage Fault Address
|
||||
uint32_t bfar = SCB->BFAR; // Bus Fault Address
|
||||
uint32_t cfsr = SCB->CFSR; // Configurable Fault Status Registers
|
||||
#endif
|
||||
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
|
||||
if ((cfsr & (1UL << 16)) != 0) // UNDEFINSTR
|
||||
{
|
||||
// For testing purposes, instead of BKPT use 'setend be'.
|
||||
if (isSemihosting (frame, AngelSWITestFaultOpCode))
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(TRACE)
|
||||
trace_printf ("[UsageFault]\n");
|
||||
dumpExceptionStack (frame, cfsr, mmfar, bfar, lr);
|
||||
#endif // defined(TRACE)
|
||||
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak))
|
||||
SVC_Handler (void)
|
||||
{
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak))
|
||||
DebugMon_Handler (void)
|
||||
{
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak))
|
||||
PendSV_Handler (void)
|
||||
{
|
||||
#if defined(DEBUG)
|
||||
__DEBUG_BKPT();
|
||||
#endif
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),weak))
|
||||
SysTick_Handler (void)
|
||||
{
|
||||
// DO NOT loop, just return.
|
||||
// Useful in case someone (like STM HAL) inadvertently enables SysTick.
|
||||
;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
76
bootloader/system/src/diag/Trace.c
Normal file
76
bootloader/system/src/diag/Trace.c
Normal file
@ -0,0 +1,76 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(TRACE)
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include "diag/Trace.h"
|
||||
#include "string.h"
|
||||
|
||||
#ifndef OS_INTEGER_TRACE_PRINTF_TMP_ARRAY_SIZE
|
||||
#define OS_INTEGER_TRACE_PRINTF_TMP_ARRAY_SIZE (128)
|
||||
#endif
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
int
|
||||
trace_printf(const char* format, ...)
|
||||
{
|
||||
int ret;
|
||||
va_list ap;
|
||||
|
||||
va_start (ap, format);
|
||||
|
||||
// TODO: rewrite it to no longer use newlib, it is way too heavy
|
||||
|
||||
static char buf[OS_INTEGER_TRACE_PRINTF_TMP_ARRAY_SIZE];
|
||||
|
||||
// Print to the local buffer
|
||||
ret = vsnprintf (buf, sizeof(buf), format, ap);
|
||||
if (ret > 0)
|
||||
{
|
||||
// Transfer the buffer to the device
|
||||
ret = trace_write (buf, (size_t)ret);
|
||||
}
|
||||
|
||||
va_end (ap);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
trace_puts(const char *s)
|
||||
{
|
||||
trace_write(s, strlen(s));
|
||||
return trace_write("\n", 1);
|
||||
}
|
||||
|
||||
int
|
||||
trace_putchar(int c)
|
||||
{
|
||||
trace_write((const char*)&c, 1);
|
||||
return c;
|
||||
}
|
||||
|
||||
void
|
||||
trace_dump_args(int argc, char* argv[])
|
||||
{
|
||||
trace_printf("main(argc=%d, argv=[", argc);
|
||||
for (int i = 0; i < argc; ++i)
|
||||
{
|
||||
if (i != 0)
|
||||
{
|
||||
trace_printf(", ");
|
||||
}
|
||||
trace_printf("\"%s\"", argv[i]);
|
||||
}
|
||||
trace_printf("]);\n");
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#endif // TRACE
|
||||
252
bootloader/system/src/diag/trace_impl.c
Normal file
252
bootloader/system/src/diag/trace_impl.c
Normal file
@ -0,0 +1,252 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(TRACE)
|
||||
|
||||
#include "cmsis_device.h"
|
||||
#include "diag/Trace.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// One of these definitions must be passed via the compiler command line
|
||||
// Note: small Cortex-M0/M0+ might implement a simplified debug interface.
|
||||
|
||||
//#define OS_USE_TRACE_ITM
|
||||
//#define OS_USE_TRACE_SEMIHOSTING_DEBUG
|
||||
//#define OS_USE_TRACE_SEMIHOSTING_STDOUT
|
||||
|
||||
#if !(defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__))
|
||||
#if defined(OS_USE_TRACE_ITM)
|
||||
#undef OS_USE_TRACE_ITM
|
||||
#warning "ITM unavailable"
|
||||
#endif // defined(OS_USE_TRACE_ITM)
|
||||
#endif // !(defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__))
|
||||
|
||||
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
|
||||
#if defined(OS_USE_TRACE_SEMIHOSTING_STDOUT) || defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
|
||||
#error "Cannot debug semihosting using semihosting trace; use OS_USE_TRACE_ITM"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// Forward definitions.
|
||||
|
||||
#if defined(OS_USE_TRACE_ITM)
|
||||
static ssize_t
|
||||
_trace_write_itm (const char* buf, size_t nbyte);
|
||||
#endif
|
||||
|
||||
#if defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
|
||||
static ssize_t
|
||||
_trace_write_semihosting_stdout(const char* buf, size_t nbyte);
|
||||
#endif
|
||||
|
||||
#if defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
|
||||
static ssize_t
|
||||
_trace_write_semihosting_debug(const char* buf, size_t nbyte);
|
||||
#endif
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
void
|
||||
trace_initialize(void)
|
||||
{
|
||||
// For regular ITM / semihosting, no inits required.
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// This function is called from _write() for fd==1 or fd==2 and from some
|
||||
// of the trace_* functions.
|
||||
|
||||
ssize_t
|
||||
trace_write (const char* buf __attribute__((unused)),
|
||||
size_t nbyte __attribute__((unused)))
|
||||
{
|
||||
#if defined(OS_USE_TRACE_ITM)
|
||||
return _trace_write_itm (buf, nbyte);
|
||||
#elif defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
|
||||
return _trace_write_semihosting_stdout(buf, nbyte);
|
||||
#elif defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
|
||||
return _trace_write_semihosting_debug(buf, nbyte);
|
||||
#endif
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(OS_USE_TRACE_ITM)
|
||||
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
// ITM is the ARM standard mechanism, running over SWD/SWO on Cortex-M3/M4
|
||||
// devices, and is the recommended setting, if available.
|
||||
//
|
||||
// The JLink probe and the GDB server fully support SWD/SWO
|
||||
// and the JLink Debugging plug-in enables it by default.
|
||||
// The current OpenOCD does not include support to parse the SWO stream,
|
||||
// so this configuration will not work on OpenOCD (will not crash, but
|
||||
// nothing will be displayed in the output console).
|
||||
|
||||
#if !defined(OS_INTEGER_TRACE_ITM_STIMULUS_PORT)
|
||||
#define OS_INTEGER_TRACE_ITM_STIMULUS_PORT (0)
|
||||
#endif
|
||||
|
||||
static ssize_t
|
||||
_trace_write_itm (const char* buf, size_t nbyte)
|
||||
{
|
||||
for (size_t i = 0; i < nbyte; i++)
|
||||
{
|
||||
// Check if ITM or the stimulus port are not enabled
|
||||
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) == 0)
|
||||
|| ((ITM->TER & (1UL << OS_INTEGER_TRACE_ITM_STIMULUS_PORT)) == 0))
|
||||
{
|
||||
return (ssize_t)i; // return the number of sent characters (may be 0)
|
||||
}
|
||||
|
||||
// Wait until STIMx is ready...
|
||||
while (ITM->PORT[OS_INTEGER_TRACE_ITM_STIMULUS_PORT].u32 == 0)
|
||||
;
|
||||
// then send data, one byte at a time
|
||||
ITM->PORT[OS_INTEGER_TRACE_ITM_STIMULUS_PORT].u8 = (uint8_t) (*buf++);
|
||||
}
|
||||
|
||||
return (ssize_t)nbyte; // all characters successfully sent
|
||||
}
|
||||
|
||||
#endif // defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
#endif // OS_USE_TRACE_ITM
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(OS_USE_TRACE_SEMIHOSTING_DEBUG) || defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
|
||||
|
||||
#include "arm/semihosting.h"
|
||||
|
||||
// Semihosting is the other output channel that can be used for the trace
|
||||
// messages. It comes in two flavours: STDOUT and DEBUG. The STDOUT channel
|
||||
// is the equivalent of the stdout in POSIX and in most cases it is forwarded
|
||||
// to the GDB server stdout stream. The debug channel is a separate
|
||||
// channel. STDOUT is buffered, so nothing is displayed until a \n;
|
||||
// DEBUG is not buffered, but can be slow.
|
||||
//
|
||||
// Choosing between semihosting stdout and debug depends on the capabilities
|
||||
// of your GDB server, and also on specific needs. It is recommended to test
|
||||
// DEBUG first, and if too slow, try STDOUT.
|
||||
//
|
||||
// The JLink GDB server fully support semihosting, and both configurations
|
||||
// are available; to activate it, use "monitor semihosting enable" or check
|
||||
// the corresponding button in the JLink Debugging plug-in.
|
||||
// In OpenOCD, support for semihosting can be enabled using
|
||||
// "monitor arm semihosting enable".
|
||||
//
|
||||
// Note: Applications built with semihosting output active normally cannot
|
||||
// be executed without the debugger connected and active, since they use
|
||||
// BKPT to communicate with the host. However, with a carefully written
|
||||
// HardFault_Handler, the semihosting BKPT calls can be processed, making
|
||||
// possible to run semihosting applications as standalone, without being
|
||||
// terminated with hardware faults.
|
||||
|
||||
#endif // OS_USE_TRACE_SEMIHOSTING_DEBUG_*
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(OS_USE_TRACE_SEMIHOSTING_STDOUT)
|
||||
|
||||
static ssize_t
|
||||
_trace_write_semihosting_stdout (const char* buf, size_t nbyte)
|
||||
{
|
||||
static int handle;
|
||||
void* block[3];
|
||||
int ret;
|
||||
|
||||
if (handle == 0)
|
||||
{
|
||||
// On the first call get the file handle from the host
|
||||
block[0] = ":tt"; // special filename to be used for stdin/out/err
|
||||
block[1] = (void*) 4; // mode "w"
|
||||
// length of ":tt", except null terminator
|
||||
block[2] = (void*) (sizeof(":tt") - 1);
|
||||
|
||||
ret = call_host (SEMIHOSTING_SYS_OPEN, (void*) block);
|
||||
if (ret == -1)
|
||||
return -1;
|
||||
|
||||
handle = ret;
|
||||
}
|
||||
|
||||
block[0] = (void*) handle;
|
||||
block[1] = (void*) buf;
|
||||
block[2] = (void*) nbyte;
|
||||
// send character array to host file/device
|
||||
ret = call_host (SEMIHOSTING_SYS_WRITE, (void*) block);
|
||||
// this call returns the number of bytes NOT written (0 if all ok)
|
||||
|
||||
// -1 is not a legal value, but SEGGER seems to return it
|
||||
if (ret == -1)
|
||||
return -1;
|
||||
|
||||
// The compliant way of returning errors
|
||||
if (ret == (int) nbyte)
|
||||
return -1;
|
||||
|
||||
// Return the number of bytes written
|
||||
return (ssize_t) (nbyte) - (ssize_t) ret;
|
||||
}
|
||||
|
||||
#endif // OS_USE_TRACE_SEMIHOSTING_STDOUT
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if defined(OS_USE_TRACE_SEMIHOSTING_DEBUG)
|
||||
|
||||
#define OS_INTEGER_TRACE_TMP_ARRAY_SIZE (16)
|
||||
|
||||
static ssize_t
|
||||
_trace_write_semihosting_debug (const char* buf, size_t nbyte)
|
||||
{
|
||||
// Since the single character debug channel is quite slow, try to
|
||||
// optimise and send a null terminated string, if possible.
|
||||
if (buf[nbyte] == '\0')
|
||||
{
|
||||
// send string
|
||||
call_host (SEMIHOSTING_SYS_WRITE0, (void*) buf);
|
||||
}
|
||||
else
|
||||
{
|
||||
// If not, use a local buffer to speed things up
|
||||
char tmp[OS_INTEGER_TRACE_TMP_ARRAY_SIZE];
|
||||
size_t togo = nbyte;
|
||||
while (togo > 0)
|
||||
{
|
||||
unsigned int n = ((togo < sizeof(tmp)) ? togo : sizeof(tmp));
|
||||
unsigned int i = 0;
|
||||
for (; i < n; ++i, ++buf)
|
||||
{
|
||||
tmp[i] = *buf;
|
||||
}
|
||||
tmp[i] = '\0';
|
||||
|
||||
call_host (SEMIHOSTING_SYS_WRITE0, (void*) tmp);
|
||||
|
||||
togo -= n;
|
||||
}
|
||||
}
|
||||
|
||||
// All bytes written
|
||||
return (ssize_t) nbyte;
|
||||
}
|
||||
|
||||
#endif // OS_USE_TRACE_SEMIHOSTING_DEBUG
|
||||
|
||||
#endif // TRACE
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
16
bootloader/system/src/newlib/README.txt
Normal file
16
bootloader/system/src/newlib/README.txt
Normal file
@ -0,0 +1,16 @@
|
||||
|
||||
The following files extend or replace some of the the newlib functionality:
|
||||
|
||||
_startup.c: a customised startup sequence, written in C
|
||||
|
||||
_exit.c: a customised exit() implementation
|
||||
|
||||
_syscalls.c: local versions of the libnosys/librdimon code
|
||||
|
||||
_sbrk.c: a custom _sbrk() to match the actual linker scripts
|
||||
|
||||
assert.c: implementation for the asserion macros
|
||||
|
||||
_cxx.cpp: local versions of some C++ support, to avoid references to
|
||||
large functions.
|
||||
|
||||
50
bootloader/system/src/newlib/_cxx.cpp
Normal file
50
bootloader/system/src/newlib/_cxx.cpp
Normal file
@ -0,0 +1,50 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// These functions are redefined locally, to avoid references to some
|
||||
// heavy implementations in the standard C++ library.
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include <cstdlib>
|
||||
#include <sys/types.h>
|
||||
#include "diag/Trace.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
namespace __gnu_cxx
|
||||
{
|
||||
void
|
||||
__attribute__((noreturn))
|
||||
__verbose_terminate_handler();
|
||||
|
||||
void
|
||||
__verbose_terminate_handler()
|
||||
{
|
||||
trace_puts(__func__);
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
extern "C"
|
||||
{
|
||||
void
|
||||
__attribute__((noreturn))
|
||||
__cxa_pure_virtual();
|
||||
|
||||
void
|
||||
__cxa_pure_virtual()
|
||||
{
|
||||
trace_puts(__func__);
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
59
bootloader/system/src/newlib/_exit.c
Normal file
59
bootloader/system/src/newlib/_exit.c
Normal file
@ -0,0 +1,59 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "diag/Trace.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if !defined(DEBUG)
|
||||
extern void
|
||||
__attribute__((noreturn))
|
||||
__reset_hardware(void);
|
||||
#endif
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// Forward declaration
|
||||
|
||||
void
|
||||
_exit(int code);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// On Release, call the hardware reset procedure.
|
||||
// On Debug we just enter an infinite loop, to be used as landmark when halting
|
||||
// the debugger.
|
||||
//
|
||||
// It can be redefined in the application, if more functionality
|
||||
// is required.
|
||||
|
||||
void
|
||||
__attribute__((weak))
|
||||
_exit(int code __attribute__((unused)))
|
||||
{
|
||||
#if !defined(DEBUG)
|
||||
__reset_hardware();
|
||||
#endif
|
||||
|
||||
// TODO: write on trace
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
void
|
||||
__attribute__((weak,noreturn))
|
||||
abort(void)
|
||||
{
|
||||
trace_puts("abort(), exiting...");
|
||||
|
||||
_exit(1);
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
65
bootloader/system/src/newlib/_sbrk.c
Normal file
65
bootloader/system/src/newlib/_sbrk.c
Normal file
@ -0,0 +1,65 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <errno.h>
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
caddr_t
|
||||
_sbrk(int incr);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// The definitions used here should be kept in sync with the
|
||||
// stack definitions in the linker script.
|
||||
|
||||
caddr_t
|
||||
_sbrk(int incr)
|
||||
{
|
||||
extern char _Heap_Begin; // Defined by the linker.
|
||||
extern char _Heap_Limit; // Defined by the linker.
|
||||
|
||||
static char* current_heap_end;
|
||||
char* current_block_address;
|
||||
|
||||
if (current_heap_end == 0)
|
||||
{
|
||||
current_heap_end = &_Heap_Begin;
|
||||
}
|
||||
|
||||
current_block_address = current_heap_end;
|
||||
|
||||
// Need to align heap to word boundary, else will get
|
||||
// hard faults on Cortex-M0. So we assume that heap starts on
|
||||
// word boundary, hence make sure we always add a multiple of
|
||||
// 4 to it.
|
||||
incr = (incr + 3) & (~3); // align value to 4
|
||||
if (current_heap_end + incr > &_Heap_Limit)
|
||||
{
|
||||
// Some of the libstdc++-v3 tests rely upon detecting
|
||||
// out of memory errors, so do not abort here.
|
||||
#if 0
|
||||
extern void abort (void);
|
||||
|
||||
_write (1, "_sbrk: Heap and stack collision\n", 32);
|
||||
|
||||
abort ();
|
||||
#else
|
||||
// Heap has overflowed
|
||||
errno = ENOMEM;
|
||||
return (caddr_t) - 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
current_heap_end += incr;
|
||||
|
||||
return (caddr_t) current_block_address;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
327
bootloader/system/src/newlib/_startup.c
Normal file
327
bootloader/system/src/newlib/_startup.c
Normal file
@ -0,0 +1,327 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// This module contains the startup code for a portable embedded
|
||||
// C/C++ application, built with newlib.
|
||||
//
|
||||
// Control reaches here from the reset handler via jump or call.
|
||||
//
|
||||
// The actual steps performed by _start are:
|
||||
// - copy the initialised data region(s)
|
||||
// - clear the BSS region(s)
|
||||
// - initialise the system
|
||||
// - run the preinit/init array (for the C++ static constructors)
|
||||
// - initialise the arc/argv
|
||||
// - branch to main()
|
||||
// - run the fini array (for the C++ static destructors)
|
||||
// - call _exit(), directly or via exit()
|
||||
//
|
||||
// If OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS is defined, the
|
||||
// code is capable of initialising multiple regions.
|
||||
//
|
||||
// The normal configuration is standalone, with all support
|
||||
// functions implemented locally.
|
||||
//
|
||||
// For this to be called, the project linker must be configured without
|
||||
// the startup sequence (-nostartfiles).
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#include <stdint.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if !defined(OS_INCLUDE_STARTUP_GUARD_CHECKS)
|
||||
#define OS_INCLUDE_STARTUP_GUARD_CHECKS (1)
|
||||
#endif
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
#if !defined(OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS)
|
||||
// Begin address for the initialisation values of the .data section.
|
||||
// defined in linker script
|
||||
extern unsigned int _sidata;
|
||||
// Begin address for the .data section; defined in linker script
|
||||
extern unsigned int _sdata;
|
||||
// End address for the .data section; defined in linker script
|
||||
extern unsigned int _edata;
|
||||
|
||||
// Begin address for the .bss section; defined in linker script
|
||||
extern unsigned int __bss_start__;
|
||||
// End address for the .bss section; defined in linker script
|
||||
extern unsigned int __bss_end__;
|
||||
#else
|
||||
// The following symbols are constructs generated by the linker, indicating
|
||||
// the location of various points in the "Memory regions initialisation arrays".
|
||||
// These arrays are created by the linker via the managed linker script
|
||||
// of each RW data mechanism. It contains the load address, execution address
|
||||
// and length section and the execution and length of each BSS (zero
|
||||
// initialised) section.
|
||||
extern unsigned int __data_regions_array_start;
|
||||
extern unsigned int __data_regions_array_end;
|
||||
extern unsigned int __bss_regions_array_start;
|
||||
extern unsigned int __bss_regions_array_end;
|
||||
#endif
|
||||
|
||||
extern void
|
||||
__initialize_args (int*, char***);
|
||||
|
||||
// main() is the entry point for newlib based applications.
|
||||
// By default, there are no arguments, but this can be customised
|
||||
// by redefining __initialize_args(), which is done when the
|
||||
// semihosting configurations are used.
|
||||
extern int
|
||||
main (int argc, char* argv[]);
|
||||
|
||||
// The implementation for the exit routine; for embedded
|
||||
// applications, a system reset will be performed.
|
||||
extern void
|
||||
__attribute__((noreturn))
|
||||
_exit (int);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// Forward declarations
|
||||
|
||||
void
|
||||
_start (void);
|
||||
|
||||
void
|
||||
__initialize_data (unsigned int* from, unsigned int* region_begin,
|
||||
unsigned int* region_end);
|
||||
|
||||
void
|
||||
__initialize_bss (unsigned int* region_begin, unsigned int* region_end);
|
||||
|
||||
void
|
||||
__run_init_array (void);
|
||||
|
||||
void
|
||||
__run_fini_array (void);
|
||||
|
||||
void
|
||||
__initialize_hardware_early (void);
|
||||
|
||||
void
|
||||
__initialize_hardware (void);
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
inline void
|
||||
__attribute__((always_inline))
|
||||
__initialize_data (unsigned int* from, unsigned int* region_begin,
|
||||
unsigned int* region_end)
|
||||
{
|
||||
// Iterate and copy word by word.
|
||||
// It is assumed that the pointers are word aligned.
|
||||
unsigned int *p = region_begin;
|
||||
while (p < region_end)
|
||||
*p++ = *from++;
|
||||
}
|
||||
|
||||
inline void
|
||||
__attribute__((always_inline))
|
||||
__initialize_bss (unsigned int* region_begin, unsigned int* region_end)
|
||||
{
|
||||
// Iterate and clear word by word.
|
||||
// It is assumed that the pointers are word aligned.
|
||||
unsigned int *p = region_begin;
|
||||
while (p < region_end)
|
||||
*p++ = 0;
|
||||
}
|
||||
|
||||
// These magic symbols are provided by the linker.
|
||||
extern void
|
||||
(*__preinit_array_start[]) (void) __attribute__((weak));
|
||||
extern void
|
||||
(*__preinit_array_end[]) (void) __attribute__((weak));
|
||||
extern void
|
||||
(*__init_array_start[]) (void) __attribute__((weak));
|
||||
extern void
|
||||
(*__init_array_end[]) (void) __attribute__((weak));
|
||||
extern void
|
||||
(*__fini_array_start[]) (void) __attribute__((weak));
|
||||
extern void
|
||||
(*__fini_array_end[]) (void) __attribute__((weak));
|
||||
|
||||
// Iterate over all the preinit/init routines (mainly static constructors).
|
||||
inline void
|
||||
__attribute__((always_inline))
|
||||
__run_init_array (void)
|
||||
{
|
||||
int count;
|
||||
int i;
|
||||
|
||||
count = __preinit_array_end - __preinit_array_start;
|
||||
for (i = 0; i < count; i++)
|
||||
__preinit_array_start[i] ();
|
||||
|
||||
// If you need to run the code in the .init section, please use
|
||||
// the startup files, since this requires the code in crti.o and crtn.o
|
||||
// to add the function prologue/epilogue.
|
||||
//_init(); // DO NOT ENABE THIS!
|
||||
|
||||
count = __init_array_end - __init_array_start;
|
||||
for (i = 0; i < count; i++)
|
||||
__init_array_start[i] ();
|
||||
}
|
||||
|
||||
// Run all the cleanup routines (mainly static destructors).
|
||||
inline void
|
||||
__attribute__((always_inline))
|
||||
__run_fini_array (void)
|
||||
{
|
||||
int count;
|
||||
int i;
|
||||
|
||||
count = __fini_array_end - __fini_array_start;
|
||||
for (i = count; i > 0; i--)
|
||||
__fini_array_start[i - 1] ();
|
||||
|
||||
// If you need to run the code in the .fini section, please use
|
||||
// the startup files, since this requires the code in crti.o and crtn.o
|
||||
// to add the function prologue/epilogue.
|
||||
//_fini(); // DO NOT ENABE THIS!
|
||||
}
|
||||
|
||||
#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
|
||||
|
||||
// These definitions are used to check if the routines used to
|
||||
// clear the BSS and to copy the initialised DATA perform correctly.
|
||||
|
||||
#define BSS_GUARD_BAD_VALUE (0xCADEBABA)
|
||||
|
||||
static uint32_t volatile __attribute__ ((section(".bss_begin")))
|
||||
__bss_begin_guard;
|
||||
static uint32_t volatile __attribute__ ((section(".bss_end")))
|
||||
__bss_end_guard;
|
||||
|
||||
#define DATA_GUARD_BAD_VALUE (0xCADEBABA)
|
||||
#define DATA_BEGIN_GUARD_VALUE (0x12345678)
|
||||
#define DATA_END_GUARD_VALUE (0x98765432)
|
||||
|
||||
static uint32_t volatile __attribute__ ((section(".data_begin")))
|
||||
__data_begin_guard = DATA_BEGIN_GUARD_VALUE;
|
||||
|
||||
static uint32_t volatile __attribute__ ((section(".data_end")))
|
||||
__data_end_guard = DATA_END_GUARD_VALUE;
|
||||
|
||||
#endif // defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
|
||||
|
||||
// This is the place where Cortex-M core will go immediately after reset,
|
||||
// via a call or jump from the Reset_Handler.
|
||||
//
|
||||
// For the call to work, and for the call to __initialize_hardware_early()
|
||||
// to work, the reset stack must point to a valid internal RAM area.
|
||||
|
||||
void __attribute__ ((section(".after_vectors"),noreturn,weak))
|
||||
_start (void)
|
||||
{
|
||||
|
||||
// Initialise hardware right after reset, to switch clock to higher
|
||||
// frequency and have the rest of the initialisations run faster.
|
||||
//
|
||||
// Mandatory on platforms like Kinetis, which start with the watch dog
|
||||
// enabled and require an early sequence to disable it.
|
||||
//
|
||||
// Also useful on platform with external RAM, that need to be
|
||||
// initialised before filling the BSS section.
|
||||
|
||||
__initialize_hardware_early ();
|
||||
|
||||
// Use Old Style DATA and BSS section initialisation,
|
||||
// that will manage a single BSS sections.
|
||||
|
||||
#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
|
||||
__data_begin_guard = DATA_GUARD_BAD_VALUE;
|
||||
__data_end_guard = DATA_GUARD_BAD_VALUE;
|
||||
#endif
|
||||
|
||||
#if !defined(OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS)
|
||||
// Copy the DATA segment from Flash to RAM (inlined).
|
||||
__initialize_data(&_sidata, &_sdata, &_edata);
|
||||
#else
|
||||
|
||||
// Copy the data sections from flash to SRAM.
|
||||
for (unsigned int* p = &__data_regions_array_start;
|
||||
p < &__data_regions_array_end;)
|
||||
{
|
||||
unsigned int* from = (unsigned int *) (*p++);
|
||||
unsigned int* region_begin = (unsigned int *) (*p++);
|
||||
unsigned int* region_end = (unsigned int *) (*p++);
|
||||
|
||||
__initialize_data (from, region_begin, region_end);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
|
||||
if ((__data_begin_guard != DATA_BEGIN_GUARD_VALUE)
|
||||
|| (__data_end_guard != DATA_END_GUARD_VALUE))
|
||||
{
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
|
||||
__bss_begin_guard = BSS_GUARD_BAD_VALUE;
|
||||
__bss_end_guard = BSS_GUARD_BAD_VALUE;
|
||||
#endif
|
||||
|
||||
#if !defined(OS_INCLUDE_STARTUP_INIT_MULTIPLE_RAM_SECTIONS)
|
||||
// Zero fill the BSS section (inlined).
|
||||
__initialize_bss(&__bss_start__, &__bss_end__);
|
||||
#else
|
||||
|
||||
// Zero fill all bss segments
|
||||
for (unsigned int *p = &__bss_regions_array_start;
|
||||
p < &__bss_regions_array_end;)
|
||||
{
|
||||
unsigned int* region_begin = (unsigned int*) (*p++);
|
||||
unsigned int* region_end = (unsigned int*) (*p++);
|
||||
__initialize_bss (region_begin, region_end);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(DEBUG) && (OS_INCLUDE_STARTUP_GUARD_CHECKS)
|
||||
if ((__bss_begin_guard != 0) || (__bss_end_guard != 0))
|
||||
{
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
// Hook to continue the initialisations. Usually compute and store the
|
||||
// clock frequency in the global CMSIS variable, cleared above.
|
||||
__initialize_hardware ();
|
||||
|
||||
// Get the argc/argv (useful in semihosting configurations).
|
||||
int argc;
|
||||
char** argv;
|
||||
__initialize_args (&argc, &argv);
|
||||
|
||||
// Call the standard library initialisation (mandatory for C++ to
|
||||
// execute the constructors for the static objects).
|
||||
__run_init_array ();
|
||||
|
||||
// Call the main entry point, and save the exit code.
|
||||
int code = main (argc, argv);
|
||||
|
||||
// Run the C++ static destructors.
|
||||
__run_fini_array ();
|
||||
|
||||
_exit (code);
|
||||
|
||||
// Should never reach this, _exit() should have already
|
||||
// performed a reset.
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
1219
bootloader/system/src/newlib/_syscalls.c
Normal file
1219
bootloader/system/src/newlib/_syscalls.c
Normal file
File diff suppressed because it is too large
Load Diff
55
bootloader/system/src/newlib/assert.c
Normal file
55
bootloader/system/src/newlib/assert.c
Normal file
@ -0,0 +1,55 @@
|
||||
//
|
||||
// This file is part of the µOS++ III distribution.
|
||||
// Copyright (c) 2014 Liviu Ionescu.
|
||||
//
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "diag/Trace.h"
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
void
|
||||
__attribute__((noreturn))
|
||||
__assert_func (const char *file, int line, const char *func,
|
||||
const char *failedexpr)
|
||||
{
|
||||
trace_printf ("assertion \"%s\" failed: file \"%s\", line %d%s%s\n",
|
||||
failedexpr, file, line, func ? ", function: " : "",
|
||||
func ? func : "");
|
||||
abort ();
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
// This is STM32 specific, but can be used on other platforms too.
|
||||
// If you need it, add the following to your application header:
|
||||
|
||||
//#ifdef USE_FULL_ASSERT
|
||||
//#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
//void assert_failed(uint8_t* file, uint32_t line);
|
||||
//#else
|
||||
//#define assert_param(expr) ((void)0)
|
||||
//#endif // USE_FULL_ASSERT
|
||||
|
||||
#if defined(USE_FULL_ASSERT)
|
||||
|
||||
void
|
||||
assert_failed (uint8_t* file, uint32_t line);
|
||||
|
||||
// Called from the assert_param() macro, usually defined in the stm32f*_conf.h
|
||||
void
|
||||
__attribute__((noreturn, weak))
|
||||
assert_failed (uint8_t* file, uint32_t line)
|
||||
{
|
||||
trace_printf ("assert_param() failed: file \"%s\", line %d\n", file, line);
|
||||
abort ();
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
#endif // defined(USE_FULL_ASSERT)
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
@ -0,0 +1,3 @@
|
||||
These files are from stsw-stm32108.zip, the folder:
|
||||
|
||||
STM32F30x_DSP_StdPeriph_Lib_V1.0.0/Libraries/STM32F30x_StdPeriph_Driver/src
|
||||
2467
bootloader/system/src/stm32f3-stdperiph/stm32f30x_adc.c
Normal file
2467
bootloader/system/src/stm32f3-stdperiph/stm32f30x_adc.c
Normal file
File diff suppressed because it is too large
Load Diff
1651
bootloader/system/src/stm32f3-stdperiph/stm32f30x_can.c
Normal file
1651
bootloader/system/src/stm32f3-stdperiph/stm32f30x_can.c
Normal file
File diff suppressed because it is too large
Load Diff
503
bootloader/system/src/stm32f3-stdperiph/stm32f30x_comp.c
Normal file
503
bootloader/system/src/stm32f3-stdperiph/stm32f30x_comp.c
Normal file
@ -0,0 +1,503 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_comp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the 7 analog comparators (COMP1, COMP2...COMP7) peripheral:
|
||||
* + Comparators configuration
|
||||
* + Window mode control
|
||||
*
|
||||
@verbatim
|
||||
|
||||
==============================================================================
|
||||
##### COMP Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The device integrates 7 analog comparators COMP1, COMP2...COMP7:
|
||||
(#) The non inverting input and inverting input can be set to GPIO pins
|
||||
as shown in table1. COMP Inputs below.
|
||||
|
||||
(#) The COMP output is internally is available using COMP_GetOutputLevel()
|
||||
and can be set on GPIO pins. Refer to table 2. COMP Outputs below.
|
||||
|
||||
(#) The COMP output can be redirected to embedded timers (TIM1, TIM2, TIM3...)
|
||||
Refer to table 3. COMP Outputs redirection to embedded timers below.
|
||||
|
||||
(#) The comparators COMP1 and COMP2, COMP3 and COMP4, COMP5 and COMP6 can be combined in window
|
||||
mode and only COMP1, COMP3 and COMP5 non inverting input can be used as non-inverting input.
|
||||
|
||||
(#) The seven comparators have interrupt capability with wake-up
|
||||
from Sleep and Stop modes (through the EXTI controller):
|
||||
(++) COMP1 is internally connected to EXTI Line 21
|
||||
(++) COMP2 is internally connected to EXTI Line 22
|
||||
(++) COMP3 is internally connected to EXTI Line 29
|
||||
(++) COMP4 is internally connected to EXTI Line 30
|
||||
(++) COMP5 is internally connected to EXTI Line 31
|
||||
(++) COMP6 is internally connected to EXTI Line 32
|
||||
(++) COMP7 is internally connected to EXTI Line 33
|
||||
|
||||
[..] Table 1. COMP Inputs
|
||||
+------------------------------------------------------------------------------------------+
|
||||
| | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|-----------------|----------------|---------------|---------------------------------------|
|
||||
| | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | DAC1 OUT (PA4) | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | DAC2 OUT (PA5) | OK | OK | OK | OK | OK | OK | OK |
|
||||
| | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 |
|
||||
| | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- |
|
||||
|-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
|
||||
| Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 |
|
||||
| Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 |
|
||||
+------------------------------------------------------------------------------------------+
|
||||
|
||||
[..] Table 2. COMP Outputs
|
||||
+-------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|-------|-------|-------|-------|-------|-------|-------|
|
||||
| PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 |
|
||||
| PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
|
||||
| PA6 | PA12 | --- | --- | --- | --- | --- |
|
||||
| PA11 | PB9 | --- | --- | --- | --- | --- |
|
||||
| PB8 | --- | --- | --- | --- | --- | --- |
|
||||
+-------------------------------------------------------+
|
||||
|
||||
[..] Table 3. COMP Outputs redirection to embedded timers
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
|
||||
| TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN |
|
||||
| | | | | | | |
|
||||
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN |
|
||||
| | | | | | | |
|
||||
| TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
|
||||
| + | + | + | + | + | + | + |
|
||||
| TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 | TIM8BKIN2 |
|
||||
| | | | | | | |
|
||||
| TIM1 OCREFCLR | TIM1 OCREFCLR | TIM1 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM8 OCREFCLR | TIM1 OCREFCLR |
|
||||
| | | | | | | |
|
||||
| TIM1 IC1 | TIM1 IC1 | TIM2 OCREFCLR | TIM3 IC3 | TIM2 IC1 | TIM2 IC2 | TIM8 OCREFCLR |
|
||||
| | | | | | | |
|
||||
| TIM2 IC4 | TIM2 IC4 | TIM3 IC2 | TIM3 OCREFCLR | TIM3 OCREFCLR | TIM2 OCREFCLR | TIM2 IC3 |
|
||||
| | | | | | | |
|
||||
| TIM2 OCREFCLR | TIM2 OCREFCLR | TIM4 IC1 | TIM4 IC2 | TIM4 IC3 | TIM16 OCREFCLR| TIM1 IC2 |
|
||||
| | | | | | | |
|
||||
| TIM3 IC1 | TIM3 IC1 | TIM15 IC1 | TIM15 OCREFCLR| TIM16 BKIN | TIM16 IC1 | TIM17 OCREFCLR|
|
||||
| | | | | | | |
|
||||
| TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
[..] Table 4. COMP Outputs blanking sources
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|
||||
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
|
||||
| TIM1 OC5 | TIM1 OC5 | TIM1 OC5 | TIM3 OC4 | TIM3 OC3 | TIM2 OC4 | TIM1 OC5 |
|
||||
| | | | | | | |
|
||||
| TIM2 OC3 | TIM2 OC3 | -------- | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 | TIM8 OC5 |
|
||||
| | | | | | | |
|
||||
| TIM3 OC3 | TIM3 OC3 | TIM2 OC4 | TIM15 OC1 | TIM8 BKIN | TIM15 OC2 | TIM15 OC2 |
|
||||
| | | | | | | |
|
||||
+----------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions to configure and program the Comparators
|
||||
of all STM32F30x devices.
|
||||
|
||||
To use the comparator, perform the following steps:
|
||||
|
||||
(#) Enable the SYSCFG APB clock to get write access to comparator
|
||||
register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
|
||||
(#) Configure the comparator input in analog mode using GPIO_Init()
|
||||
|
||||
(#) Configure the comparator output in alternate function mode
|
||||
using GPIO_Init() and use GPIO_PinAFConfig() function to map the
|
||||
comparator output to the GPIO pin
|
||||
|
||||
(#) Configure the comparator using COMP_Init() function:
|
||||
(++) Select the inverting input
|
||||
(++) Select the non-inverting input
|
||||
(++) Select the output polarity
|
||||
(++) Select the output redirection
|
||||
(++) Select the hysteresis level
|
||||
(++) Select the power mode
|
||||
|
||||
(#) Enable the comparator using COMP_Cmd() function
|
||||
|
||||
(#) If required enable the COMP interrupt by configuring and enabling
|
||||
EXTI line in Interrupt mode and selecting the desired sensitivity
|
||||
level using EXTI_Init() function. After that enable the comparator
|
||||
interrupt vector using NVIC_Init() function.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_comp.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP
|
||||
* @brief COMP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* CSR register Mask */
|
||||
#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00000003)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes COMP peripheral registers to their default reset values.
|
||||
* @note Deinitialization can't be performed if the COMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_DeInit(uint32_t COMP_Selection)
|
||||
{
|
||||
/*!< Set COMP_CSR register to reset value */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) = ((uint32_t)0x00000000);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP peripheral according to the specified parameters
|
||||
* in COMP_InitStruct
|
||||
* @note If the selected comparator is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @note By default, PA1 is selected as COMP1 non inverting input.
|
||||
* To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
|
||||
* the configuration information for the specified COMP peripheral.
|
||||
* - COMP_InvertingInput specifies the inverting input of COMP
|
||||
* - COMP_NonInvertingInput specifies the non inverting input of COMP
|
||||
* - COMP_Output connect COMP output to selected timer
|
||||
* input (Input capture / Output Compare Reference Clear / Break Input)
|
||||
* - COMP_BlankingSrce specifies the blanking source of COMP
|
||||
* - COMP_OutputPol select output polarity
|
||||
* - COMP_Hysteresis configures COMP hysteresis value
|
||||
* - COMP_Mode configures COMP power mode
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
|
||||
assert_param(IS_COMP_NONINVERTING_INPUT(COMP_InitStruct->COMP_NonInvertingInput));
|
||||
assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
|
||||
assert_param(IS_COMP_BLANKING_SOURCE(COMP_InitStruct->COMP_BlankingSrce));
|
||||
assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
|
||||
assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
|
||||
assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
|
||||
|
||||
/*!< Get the COMPx_CSR register value */
|
||||
tmpreg = *(__IO uint32_t *) (COMP_BASE + COMP_Selection);
|
||||
|
||||
/*!< Clear the COMP1SW1, COMPxINSEL, COMPxOUTSEL, COMPxPOL, COMPxHYST and COMPxMODE bits */
|
||||
tmpreg &= (uint32_t) (COMP_CSR_CLEAR_MASK);
|
||||
|
||||
/*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
|
||||
/*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
|
||||
/*!< Set COMPxNONINSEL bits according to COMP_InitStruct->COMP_NonInvertingInput value */
|
||||
/*!< Set COMPxBLANKING bits according to COMP_InitStruct->COMP_BlankingSrce value */
|
||||
/*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
|
||||
/*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
|
||||
/*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
|
||||
/*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
|
||||
tmpreg |= (uint32_t)(COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_NonInvertingInput |
|
||||
COMP_InitStruct->COMP_Output | COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_BlankingSrce |
|
||||
COMP_InitStruct->COMP_Hysteresis | COMP_InitStruct->COMP_Mode);
|
||||
|
||||
/*!< Write to COMPx_CSR register */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each COMP_InitStruct member with its default value.
|
||||
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
|
||||
{
|
||||
COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
|
||||
COMP_InitStruct->COMP_NonInvertingInput = COMP_NonInvertingInput_IO1;
|
||||
COMP_InitStruct->COMP_Output = COMP_Output_None;
|
||||
COMP_InitStruct->COMP_BlankingSrce = COMP_BlankingSrce_None;
|
||||
COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
|
||||
COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
|
||||
COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the COMP peripheral.
|
||||
* @note If the selected comparator is locked, enable/disable can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @param NewState: new state of the COMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* When enabled, the comparator compares the non inverting input with
|
||||
* the inverting input and the comparison result is available
|
||||
* on comparator output.
|
||||
* When disabled, the comparator doesn't perform comparison and the
|
||||
* output level is low.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected COMPx peripheral */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxEN);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected COMP peripheral */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Close or Open the SW1 switch.
|
||||
* @note If the COMP1 is locked, Close/Open the SW1 switch can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @note This switch is solely intended to redirect signals onto high
|
||||
* impedance input, such as COMP1 non-inverting input (highly resistive switch)
|
||||
* @param NewState: New state of the analog switch.
|
||||
* This parameter can be
|
||||
* ENABLE so the SW1 is closed; PA1 is connected to PA4
|
||||
* or DISABLE so the SW1 switch is open; PA1 is disconnected from PA4
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Close SW1 switch */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMP1SW1);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open SW1 switch */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMP1SW1);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) of the selected comparator.
|
||||
* The output level depends on the selected polarity.
|
||||
* If the polarity is not inverted:
|
||||
* - Comparator output is low when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is high when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* If the polarity is inverted:
|
||||
* - Comparator output is high when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* - Comparator output is low when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @retval Returns the selected comparator output level: low or high.
|
||||
*
|
||||
*/
|
||||
uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
|
||||
{
|
||||
uint32_t compout = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
/* Check if selected comparator output is high */
|
||||
if ((*(__IO uint32_t *) (COMP_BASE + COMP_Selection) & (COMP_CSR_COMPxOUT)) != 0)
|
||||
{
|
||||
compout = COMP_OutputLevel_High;
|
||||
}
|
||||
else
|
||||
{
|
||||
compout = COMP_OutputLevel_Low;
|
||||
}
|
||||
|
||||
/* Return the comparator output level */
|
||||
return (uint32_t)(compout);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group2 Window mode control function
|
||||
* @brief Window mode control function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Window mode control function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the window mode.
|
||||
* Window mode for comparators makes use of two comparators:
|
||||
* COMP1 and COM2, COMP3 and COMP4, COMP5 and COMP6.
|
||||
* In window mode, COMPx and COMPx-1 (where x can be 2, 4 or 6)
|
||||
* non inverting inputs are connected together and only COMPx-1 non
|
||||
* inverting input can be used.
|
||||
* e.g When window mode enabled for COMP4, COMP3 non inverting input (PB14 or PD14)
|
||||
* is to be used.
|
||||
* @note If the COMPx is locked, ENABLE/DISABLE the window mode can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 2, 4 or 6
|
||||
* to select the COMP peripheral.
|
||||
* param NewState: new state of the window mode.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* When enbaled, COMPx and COMPx-1 non inverting inputs are connected together.
|
||||
* When disabled, COMPx and COMPx-1 non inverting inputs are disconnected.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_COMP_WINDOW(COMP_Selection));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the window mode */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) COMP_CSR_COMPxWNDWEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the window mode */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) &= (uint32_t)(~COMP_CSR_COMPxWNDWEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group3 COMP configuration locking function
|
||||
* @brief COMP1, COMP2,...COMP7 configuration locking function
|
||||
* COMP1, COMP2,...COMP7 configuration can be locked each separately.
|
||||
* Unlocking is performed by system reset.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration Lock function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected comparator (COMP1/COMP2) configuration.
|
||||
* @note Locking the configuration means that all control bits are read-only.
|
||||
* To unlock the comparator configuration, perform a system reset.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be COMP_Selection_COMPx where x can be 1 to 7
|
||||
* to select the COMP peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_LockConfig(uint32_t COMP_Selection)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
/* Set the lock bit corresponding to selected comparator */
|
||||
*(__IO uint32_t *) (COMP_BASE + COMP_Selection) |= (uint32_t) (COMP_CSR_COMPxLOCK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
354
bootloader/system/src/stm32f3-stdperiph/stm32f30x_crc.c
Normal file
354
bootloader/system/src/stm32f3-stdperiph/stm32f30x_crc.c
Normal file
@ -0,0 +1,354 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f30x_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 23-October-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of CRC computation unit peripheral:
|
||||
* + Configuration of the CRC computation unit
|
||||
* + CRC computation of one/many 32-bit data
|
||||
* + CRC Independent register (IDR) access
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(#) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
|
||||
function.
|
||||
(#) Select the polynomial size: 7-bit, 8-bit, 16-bit or 32-bit.
|
||||
(#) Set the polynomial coefficients using CRC_SetPolynomial();
|
||||
(#) If required, select the reverse operation on input data
|
||||
using CRC_ReverseInputDataSelect();
|
||||
(#) If required, enable the reverse operation on output data
|
||||
using CRC_ReverseOutputDataCmd(Enable);
|
||||
(#) If required, set the initialization remainder value using
|
||||
CRC_SetInitRegister();
|
||||
(#) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
|
||||
or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit
|
||||
data buffer.
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f30x_crc.h"
|
||||
|
||||
/** @addtogroup STM32F30x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
|
||||
* @brief Configuration of the CRC computation unit functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### CRC configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes CRC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_DeInit(void)
|
||||
{
|
||||
/* Set DR register to reset value */
|
||||
CRC->DR = 0xFFFFFFFF;
|
||||
/* Set the POL register to the reset value: 0x04C11DB7 */
|
||||
CRC->POL = 0x04C11DB7;
|
||||
/* Reset IDR register */
|
||||
CRC->IDR = 0x00;
|
||||
/* Set INIT register to reset value */
|
||||
CRC->INIT = 0xFFFFFFFF;
|
||||
/* Reset the CRC calculation unit */
|
||||
CRC->CR = CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets the CRC calculation unit and sets INIT register content in DR register.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ResetDR(void)
|
||||
{
|
||||
/* Reset CRC generator */
|
||||
CRC->CR |= CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the polynomial size.
|
||||
* @param CRC_PolSize: Specifies the polynomial size.
|
||||
* This parameter can be:
|
||||
* @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
|
||||
* @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
|
||||
* @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
|
||||
* @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
|
||||
{
|
||||
uint32_t tmpcr = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
|
||||
|
||||
/* Get CR register value */
|
||||
tmpcr = CRC->CR;
|
||||
|
||||
/* Reset POL_SIZE bits */
|
||||
tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
|
||||
/* Set the polynomial size */
|
||||
tmpcr |= (uint32_t)CRC_PolSize;
|
||||
|
||||
/* Write to CR register */
|
||||
CRC->CR = (uint32_t)tmpcr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the reverse operation to be performed on input data.
|
||||
* @param CRC_ReverseInputData: Specifies the reverse operation on input data.
|
||||
* This parameter can be:
|
||||
* @arg CRC_ReverseInputData_No: No reverse operation is performed
|
||||
* @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
|
||||
* @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
|
||||
* @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
|
||||
{
|
||||
uint32_t tmpcr = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
|
||||
|
||||
/* Get CR register value */
|
||||
tmpcr = CRC->CR;
|
||||
|
||||
/* Reset REV_IN bits */
|
||||
tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
|
||||
/* Set the reverse operation */
|
||||
tmpcr |= (uint32_t)CRC_ReverseInputData;
|
||||
|
||||
/* Write to CR register */
|
||||
CRC->CR = (uint32_t)tmpcr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disable the reverse operation on output data.
|
||||
* The reverse operation on output data is performed on 32-bit.
|
||||
* @param NewState: new state of the reverse operation on output data.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ReverseOutputDataCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable reverse operation on output data */
|
||||
CRC->CR |= CRC_CR_REV_OUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable reverse operation on output data */
|
||||
CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the INIT register.
|
||||
* @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register
|
||||
* @param CRC_InitValue: Programmable initial CRC value
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetInitRegister(uint32_t CRC_InitValue)
|
||||
{
|
||||
CRC->INIT = CRC_InitValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the polynomail coefficients.
|
||||
* @param CRC_Pol: Polynomial to be used for CRC calculation.
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetPolynomial(uint32_t CRC_Pol)
|
||||
{
|
||||
CRC->POL = CRC_Pol;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
|
||||
* @brief CRC computation of one/many 32-bit data functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### CRC computation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||
* @param CRC_Data: data word(32-bit) to compute its CRC
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC(uint32_t CRC_Data)
|
||||
{
|
||||
CRC->DR = CRC_Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 16-bit CRC of a given 16-bit data.
|
||||
* @param CRC_Data: data half-word(16-bit) to compute its CRC
|
||||
* @retval 16-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
|
||||
{
|
||||
*(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 8-bit CRC of a given 8-bit data.
|
||||
* @param CRC_Data: 8-bit data to compute its CRC
|
||||
* @retval 8-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
|
||||
{
|
||||
*(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
CRC->DR = pBuffer[index];
|
||||
}
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current CRC value.
|
||||
* @param None
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_GetCRC(void)
|
||||
{
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
|
||||
* @brief CRC Independent Register (IDR) access (write/read) functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### CRC Independent Register (IDR) access functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Stores an 8-bit data in the Independent Data(ID) register.
|
||||
* @param CRC_IDValue: 8-bit value to be stored in the ID register
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetIDRegister(uint8_t CRC_IDValue)
|
||||
{
|
||||
CRC->IDR = CRC_IDValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
|
||||
* @param None
|
||||
* @retval 8-bit value of the ID register
|
||||
*/
|
||||
uint8_t CRC_GetIDRegister(void)
|
||||
{
|
||||
return (CRC->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user